Multiple address translations

• US 6,732,250 B2
• Filed: 02/08/2002
• Issued: 05/04/2004
• Est. Priority Date: 07/31/2001
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Durrant, Paul
• Primary Examiner(s): MCLEAN MAYO, KIMBERLY N
• Application Number:
  US10/071,045
• Publication Number:
  US 20030028746A1
• Time in Patent Office: 816 Days
• Field of Search: 711/202, 711/200, 711/205, 711/206, 711/207, 711/162, 711/221, 711/203
• US Class Current: 711/202
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/2087 with a common controller
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Abstract

A computer system includes memory and at least a first processor that includes a memory management unit. The memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses. The translation table entries provide first and second memory address translations for a processor address. The memory management unit can enable either the first translation or the second translation to be used in response to a processor address to enable data to be written simultaneously to different memories or parts of a memory. A first translation addresses could be for a first memory and a second translation addresses could be for a second backup memory. The backup memory could then be used in the event of a fault.

Claims

1. A computer system comprising memory and at least a first processor that includes a memory management unit, which memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses with at least one translation table entry providing at least a first memory address translation and a second, different, memory address translation for a processor address, wherein the memory management unit is operable selectively to enable both the first translation and the second translation to be used in response to the processor address to provide simultaneous addressing of different parts of memory.

2. The computer system of claim 1, wherein all translation entries provide first and second translations for a processor address.

3. The computer system of claim 1, wherein the memory management unit is operable selectively to enable either the first translation or the second translation to be used in response to the processor address, to provide selectable addressing of different parts of memory.

4. The computer system of claim 1, wherein the memory management unit is programmable on a per translation basis to determine which of the one or more translations are to be active to provide addressing of different parts of memory.

5. The computer system of claim 1, wherein the memory management unit includes status storage containing indicators as to which of the first translation and the second translations are to be used in response to a processor address.

6. The computer system of claim 1, wherein the first translation addresses a first memory and the second translation addresses a second memory, separate from the first memory.

7. The computer system of claim 6, wherein the first memory is a memory local to the first processor and the second memory is a memory local to a second processor interconnected to the first processor via an interconnection.

8. The computer system of claim 7, wherein the interconnection is a bridge that interconnects an IO bus of the first processor to an IO bus of the second processor.

9. The computer system of claim 6, wherein the memory management unit is operable in response to a replication instruction at a processor address to read from a first memory location in the first memory identified by the first translation for the processor address and to write to a second memory location in the second memory identified by the second translation for the processor address.

10. The computer system of claim 6, wherein the memory management unit is operable in response to a replication instruction at a processor address to read from a first memory location in the first memory identified by the first translation for the processor address and to write to the first memory identified by the first translation and to a second memory location in the second memory identified by the second translation for the processor address.

11. The computer system of claim 6, wherein the first memory is a main memory for the first processor and the second memory is a backup memory.

12. The computer system of claim 10, wherein second memory is a memory local to a second processor interconnected to the first processor via an interconnection.

13. The computer system of claim 12, wherein the interconnection is a bridge that interconnects an IO bus of the first processor to an IO bus of the second processor.

14. The computer system of claim 6, wherein the memory management unit is operable in response to a read instruction at a processor address to read from a first memory location in the first memory identified by the first translation for the processor address and is operable in response to a write instruction at a processor address to write to a first memory location in the first memory identified by the first translation and to a second memory location in the second memory identified by the second translation for the processor address.

15. The computer system of claim 1, comprising a plurality of processors interconnected by an interconnection, each processor comprising a respective memory management unit that includes a translation table having translation table entries providing at least first and second memory translations for a locally generated processor address each first memory translation relating to the memory local to the processor to which the memory management unit belongs, and each second memory translation relates to the memory local to the another processor.

16. The computer system of claim 8, wherein the plurality of processors are operable in lockstep.

17. The computer system of claim 1, further comprising an IO memory management unit, the IO memory management unit including a translation table with a plurality of IO translation table entries for translating IO addresses to memory addresses, wherein at least one IO translation table entry provides at least a first memory address translation and a second, different, memory address translation for an IO address.

18. A method of generating an image of locations in a memory of a computer, the method comprising:

a first processor generating predetermined instructions identifying processor addresses; and

a memory management unit responding to a said processor address by selectively enabling both a first and a second translation of the processor address to be used in response to the processor address and providing, from a translation table entry for the processor address, said first translation for a read from a first memory location;

reading of contents of the first memory location;

the memory management unit further providing from said translation table entry for said processor address, said second translation for a write of the content of the first memory location to a second memory location;

writing of the content of the first memory location to said second memory location; and

rewriting of the content of the first memory location to the first memory location.

19. The method of claim 18, wherein the first address translation addresses a first memory and the second translation addresses a second memory, separate from the first memory.

20. The method of claim 19, wherein the first memory is a memory local to the first processor and the second memory is a memory local to a second processor interconnected to the first processor via an interconnection.

21. The method of claim 20, wherein the interconnection is a bridge that interconnects an IO bus of the first processor to an IO bus of the second processor.

22. The method of claim 21, wherein the first memory is a main memory for the first processor and the second memory is a backup memory.

23. The method of claim 22, wherein second memory is a memory local to a second processor interconnected to the first processor via an interconnection.

24. The method of claim 18, wherein a plurality of processors are interconnected by an interconnection, each processor comprising a respective memory management unit that includes a translation table having translation table entries providing at least first and second memory translations for a locally generated processor address each first memory translation relating to the memory local to the processor to which the memory management unit belongs, and each second memory translation relates to the memory local to the another processor.

25. The method of claim 24, wherein the interconnection is a bridge that interconnects an IO bus of each of the processors.

26. The method of claim 24, operable to establish an equivalent memory state in the local memory of each of the processors, whereinafter the processors are operable in lockstep.

27. A computer system comprising memory means and at least first processor means that include a memory management means, which memory management means includes translation table means having a plurality of translation table entries for translating processor addresses to memory addresses with at least one translation table entry providing at least a first memory address translation and a second, different, memory address translation for a processor address, wherein the memory management means is operable selectively to enable both the first translation and the second translation to be used in response to the processor address to provide simultaneous addressing of different parts of memory.

28. A method of managing memory in a computer system, the method comprising providing a translation table having a plurality of translation table entries for translating processor addresses to memory addresses with at least one translation table entry providing at least a first memory address translation and a second, different, memory address translation for a processor address, and selectively enabling both the first translation and the second translation to be used in response to the processor address to provide simultaneous addressing of different parts of memory.

29. A computer system comprising memory and at least a first processor that includes a memory management unit, which memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses with at least one translation table entry providing at least a first memory address translation and a second, different, memory address translation for a processor address, wherein the first translation addresses a first memory and the second translation addresses a second memory, separate from the first memory and wherein the memory management unit is operable in response to a replication instruction at a processor address to read from a first memory location in the first memory identified by the first translation for the processor address and to write to a second memory location in the second memory identified by the second translation for the processor address.

30. A computer system comprising memory and at least a first processor that includes a memory management unit, which memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses with at least one translation table entry providing at least a first memory address translation and a second, different, memory address translation for a processor address, wherein the first translation addresses a first memory and the second translation addresses a second memory, separate from the first memory and, wherein the memory management unit is operable in response to a replication instruction at a processor address to read from a first memory location in the first memory identified by the first translation for the processor address and to write to the first memory identified by the first translation and to a second memory location in the second memory identified by the second translation for the processor address.

31. The computer system of claim 30, wherein said second memory is a memory local to a second processor interconnected to the first processor via an interconnection.

32. The computer system of claim 31, wherein the interconnection is a bridge that interconnects an IO bus of the first processor to an IO bus of the second processor.

33. A computer system comprising memory and at least a first processor that includes a memory management unit, which memory management unit includes a translation table having a plurality of translation table entries for translating processor addresses to memory addresses with at least one translation table entry providing at least a first memory address translation and a second, different, memory address translation for a processor address, wherein the first translation addresses a first memory and the second translation addresses a second memory, separate from the first memory, and wherein the memory management unit is operable in response to a read instruction at a processor address to read from a first memory location in the first memory identified by the first translation for the processor address and is operable in response to a write instruction at a processor address to write to a first memory location in the first memory identified by the first translation and to a second memory location in the second memory identified by the second translation for the processor address.