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Nonmaskable interrupt workaround for a single exception interrupt handler processor

  • US 6,732,298 B1
  • Filed: 07/31/2000
  • Issued: 05/04/2004
  • Est. Priority Date: 07/31/2000
  • Status: Expired due to Fees
First Claim
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1. An array controller board for controlling a plurality of hard disk drives, said array controller board including a bridge logic device that couples together a processor, a memory, and a peripheral bus, comprising:

  • a critical failure signal input line to the processor asserted by a debug request from debugging computer coupled to the array controller board;

    a hardware device interrupt input line to the processor asserted by said bridge logic device, said processor programmable to disable the device interrupt input line so hardware device interrupts are not detected by said processor; and

    a ROM coupled to the bridge logic device, said processor executing software stored on the ROM that services a debug request from said debugging computer asserted on said critical failure signal input line even when the processor has disabled the hardware device interrupt input.

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