Nonmaskable interrupt workaround for a single exception interrupt handler processor

• US 6,732,298 B1
• Filed: 07/31/2000
• Issued: 05/04/2004
• Est. Priority Date: 07/31/2000
• Status: Expired due to Fees

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Sabotta, Michael L., Grieff, Thomas W., Murthy, Purna C.
• Primary Examiner(s): LE, DIEU MINH T
• Application Number:
  US09/628,747
• Time in Patent Office: 1,373 Days
• Field of Search: 714/34, 714/35, 710/48, 710/260, 710/261, 710/262, 710/263, 710/264, 710/266
• US Class Current: 714/34
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers

Abstract

A system and method is disclosed for debugging of a hardware board that includes a processor with only a single level of interrupts that are either all enabled or all disabled. The processor does not implement nonmaskable interrupts. The processor on the board contains a machine check exception (MCP) input line that permits implementation of a nonmaskable pseudo-interrupt for debugging of the hardware board. The nonmaskable pseudo-interrupt informs the processor of a debug request even when all device interrupts in the interrupt processor are disabled. A processor-to-bus bridge connected to the processor on the hardware board contains a critical interrupt register. Test equipment connected to the processor-to-bus bridge sets a bit in the critical interrupt register for requesting the nonmaskable pseudo-interrupt, the processor-to-bus bridge reading the bit in the critical interrupt register to determine whether a nonmaskable pseudo interrupt debug request has occurred. The processor-to-bus bridge asserts the MCP input line of the processor after determining that the test equipment has requested the nonmaskable pseudo-interrupt. The processor then executes handler software that communicates with the test equipment to debug the hardware board.

Claims

1. An array controller board for controlling a plurality of hard disk drives, said array controller board including a bridge logic device that couples together a processor, a memory, and a peripheral bus, comprising:

a critical failure signal input line to the processor asserted by a debug request from debugging computer coupled to the array controller board;

a hardware device interrupt input line to the processor asserted by said bridge logic device, said processor programmable to disable the device interrupt input line so hardware device interrupts are not detected by said processor; and

a ROM coupled to the bridge logic device, said processor executing software stored on the ROM that services a debug request from said debugging computer asserted on said critical failure signal input line even when the processor has disabled the hardware device interrupt input.

2. The computer system of claim 1 wherein the bridge logic device includes an interrupt status register, interrupt mask register, and a critical interrupt register.

3. The computer system of claim 2 wherein the debugging computer executes debugging software that sets a bit in the critical interrupt register for requesting service by said processor, said bridge logic device reading said bit in the critical interrupt register to determine whether to assert said critical failure signal input line.

4. A computer system, comprising:

one or more system CPUs;

a keyboard coupled to said system CPUs; and

a plurality of array controller boards coupled to said system CPUs, each of said array controllers interfacing with a set of hard disk drives, said array controllers each including a single level interrupt processor containing a critical failure signal input line asserted by a debug request from test equipment coupled to the processor to permit debugging of the array controller.

5. The computer system of claim 4 wherein assertion of the critical failure signal input line informs the processor of the debug request even when all device interrupts in the processor are disabled.

6. The computer system of claim 4 wherein the array controller further comprises a processor-to-bus bridge coupled to the single level interrupt processor, said processor-to-bus bridge including an interrupt status register, interrupt mask register, and a critical interrupt register.

7. The computer system of claim 6 wherein the test equipment sets a bit in the critical interrupt register for requesting said debug request, said processor-to-bus bridge reading said bit in the critical interrupt register to determine whether said debug request has occurred.

8. The computer system of claim 7 wherein the processor-to-bus bridge asserts a machine check exception (MCP) input line of said interrupt processor after determining that the debugging computer has requested said debug request.

9. A method of performing a nonmaskable interrupt in a computer system that includes a processor that does not have a nonmaskable interrupt input signal, comprising:

setting a bit in a critical interrupt register;

asserting a signal line of said processor that is independent of hardware device interrupts in response to setting of the bit in said critical interrupt register; and

executing a software handler in response to the assertion of the signal line, wherein the software handler includes a communication module.

10. The method of claim 9, wherein the bit in the critical interrupt register is set by test equipment coupled to the processor, said bit being set indicating to the processor that the test equipment requests a nonmaskable interrupt.

11. The method of claim 9, wherein the communication module configures the processor to communicate with test equipment through a dedicated port.

12. The method of claim 9, wherein the communication module is executed only if said critical interrupt register bit is set.

13. An array controller board that comprises:

means for servicing interrupts from devices on the array controller board;

means for asserting an interrupt line to said means for servicing, said means for asserting including a critical interrupt register,

wherein said means for asserting asserts a critical failure signal line to the means for servicing when a bit in the critical interrupt register is set; and

wherein after the critical failure signal line is asserted, said means for servicing enables communication with test equipment.

14. An array controller board, comprising:

a processor;

a plurality of hardware interrupts that collectively are enabled or disabled;

bridge logic coupled to the processor; and

a connector to which test equipment external to the array controller board can be connected;

wherein, upon connecting the test equipment to the connector, a bit is set in the bridge logic and in response to the bit being set, a critical failure signal is asserted by the bridge to the processor to indicate that a debug event is to occur;

wherein the critical failure signal also is configured to be asserted upon an occurrence of a catastrophic failure on the array controller board.

15. The array controller board of claim 14 wherein the critical failure signal is asserted even if the plurality of hardware interrupts are all disabled.