Nonmaskable interrupt workaround for a single exception interrupt handler processor
First Claim
1. An array controller board for controlling a plurality of hard disk drives, said array controller board including a bridge logic device that couples together a processor, a memory, and a peripheral bus, comprising:
- a critical failure signal input line to the processor asserted by a debug request from debugging computer coupled to the array controller board;
a hardware device interrupt input line to the processor asserted by said bridge logic device, said processor programmable to disable the device interrupt input line so hardware device interrupts are not detected by said processor; and
a ROM coupled to the bridge logic device, said processor executing software stored on the ROM that services a debug request from said debugging computer asserted on said critical failure signal input line even when the processor has disabled the hardware device interrupt input.
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Accused Products
Abstract
A system and method is disclosed for debugging of a hardware board that includes a processor with only a single level of interrupts that are either all enabled or all disabled. The processor does not implement nonmaskable interrupts. The processor on the board contains a machine check exception (MCP) input line that permits implementation of a nonmaskable pseudo-interrupt for debugging of the hardware board. The nonmaskable pseudo-interrupt informs the processor of a debug request even when all device interrupts in the interrupt processor are disabled. A processor-to-bus bridge connected to the processor on the hardware board contains a critical interrupt register. Test equipment connected to the processor-to-bus bridge sets a bit in the critical interrupt register for requesting the nonmaskable pseudo-interrupt, the processor-to-bus bridge reading the bit in the critical interrupt register to determine whether a nonmaskable pseudo interrupt debug request has occurred. The processor-to-bus bridge asserts the MCP input line of the processor after determining that the test equipment has requested the nonmaskable pseudo-interrupt. The processor then executes handler software that communicates with the test equipment to debug the hardware board.
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Citations
15 Claims
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1. An array controller board for controlling a plurality of hard disk drives, said array controller board including a bridge logic device that couples together a processor, a memory, and a peripheral bus, comprising:
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a critical failure signal input line to the processor asserted by a debug request from debugging computer coupled to the array controller board;
a hardware device interrupt input line to the processor asserted by said bridge logic device, said processor programmable to disable the device interrupt input line so hardware device interrupts are not detected by said processor; and
a ROM coupled to the bridge logic device, said processor executing software stored on the ROM that services a debug request from said debugging computer asserted on said critical failure signal input line even when the processor has disabled the hardware device interrupt input. - View Dependent Claims (2, 3)
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4. A computer system, comprising:
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one or more system CPUs;
a keyboard coupled to said system CPUs; and
a plurality of array controller boards coupled to said system CPUs, each of said array controllers interfacing with a set of hard disk drives, said array controllers each including a single level interrupt processor containing a critical failure signal input line asserted by a debug request from test equipment coupled to the processor to permit debugging of the array controller. - View Dependent Claims (5, 6, 7, 8)
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9. A method of performing a nonmaskable interrupt in a computer system that includes a processor that does not have a nonmaskable interrupt input signal, comprising:
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setting a bit in a critical interrupt register;
asserting a signal line of said processor that is independent of hardware device interrupts in response to setting of the bit in said critical interrupt register; and
executing a software handler in response to the assertion of the signal line, wherein the software handler includes a communication module. - View Dependent Claims (10, 11, 12)
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13. An array controller board that comprises:
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means for servicing interrupts from devices on the array controller board;
means for asserting an interrupt line to said means for servicing, said means for asserting including a critical interrupt register, wherein said means for asserting asserts a critical failure signal line to the means for servicing when a bit in the critical interrupt register is set; and
wherein after the critical failure signal line is asserted, said means for servicing enables communication with test equipment.
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14. An array controller board, comprising:
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a processor;
a plurality of hardware interrupts that collectively are enabled or disabled;
bridge logic coupled to the processor; and
a connector to which test equipment external to the array controller board can be connected;
wherein, upon connecting the test equipment to the connector, a bit is set in the bridge logic and in response to the bit being set, a critical failure signal is asserted by the bridge to the processor to indicate that a debug event is to occur;
wherein the critical failure signal also is configured to be asserted upon an occurrence of a catastrophic failure on the array controller board. - View Dependent Claims (15)
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Specification