Method for designing a semiconductor integrated circuit which includes consideration of parasitic elements on critical data paths

• US 6,732,340 B1
• Filed: 07/20/2000
• Issued: 05/04/2004
• Est. Priority Date: 07/26/1999
• Status: Expired due to Fees

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Akashi, Teruo
• Primary Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US09/620,219
• Time in Patent Office: 1,384 Days
• Field of Search: 716/5, 716/6, 716/4, 716/7, 716/8
• US Class Current: 716/113
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

In a layout data forming step and a layout outputting step after a netlist is read, layout data is formed based on the netlist. In a path sorting step in parallel with these steps, a delay for each path is calculated based on the netlist to compare with a predetermined delay. Only a path having a delay exceeding the predetermined delay is output as a target path to an extraction path file. Then in a parasitic element extracting step, parasitic elements are extracted only from a graphic pattern included in the target path in the layout data while referencing the extraction path file.

Claims

1. A method for designing a semiconductor integrated circuit, which includes multiple circuit elements and multiple paths interconnecting those elements together, by extracting parasitic elements, associated with at least one of the paths, from the circuit to analyze operation timing of the circuit elements, the method comprising the steps of:

a) forming graphic patterns for the multiple circuit elements and laying out the graphic patterns according to a netlist describing topology information about interconnections among the circuit elements, thereby generating layout data including information about wire lengths;

b) estimating wire lengths of interconnection lines included in each of the paths in accordance with the layout data, comparing said estimated wire lengths of said paths to a predetermined length, and selecting based on said comparison at least one of the paths which has an estimated wire length exceeding said predetermined length as a target path; and

c) extracting the parasitic elements from at least one of the graphic patterns, which correspond to the target path.

2. The method of claim 1, wherein the step b) comprises the step of sorting out at least one of the paths, which is expected to cause a delay exceeding a predetermined amount of time, as a second target path.

3. The method of claim 1, wherein each path having an estimated wire length exceeding said predetermined length is identified as a target path, and parasitic elements are extracted for each target path.

4. The method of claim 1, wherein each comparison is performed utilizing the same predetermined length.

5. A method for designing a semiconductor integrated circuit, which includes multiple circuit elements and multiple paths interconnecting those elements together, by extracting parasitic elements, associated with at least one of the paths, from the circuit to analyze operation timing of the circuit elements, the method comprising the steps of:

a) forming graphic patterns for the multiple circuit elements and laying out the graphic patterns according to a netlist describing topology information about interconnections among the circuit elements, thereby generating layout data including information about wire lengths;

b) estimating the length of pairs of interconnection lines, which are included in two adjacent ones of the paths and are substantially parallel to each other, comparing the estimated length of said pairs of interconnection lines to a predetermined length, and selecting based on said comparison at least two of the paths, in which the estimated length of the parallel interconnection lines exceeds said predetermined length, as target paths; and

c) extracting the parasitic elements from at least one of the graphic patterns, which correspond to the target paths.

6. The method of claim 5, wherein the step b) comprises the step of sorting out at least one of the paths, which is expected to cause a delay exceeding a predetermined amount of time, as another target path.

7. A method for designing a semiconductor integrated circuit, which includes multiple circuit elements and multiple paths interconnecting those elements together, by extracting parasitic elements, associated with at least one of the paths, from the circuit to analyze operation timing of the circuit elements, the method comprising the steps of:

a) estimating delays, which will be caused by the respective paths, according to a netlist describing topology information about interconnections among the circuit elements;

b) forming graphic patterns for the multiple circuit elements and laying out the graphic patterns according to the netlist, thereby generating layout data;

c) selecting at least one of the paths, of which the estimated delay exceeds a predetermined amount of time based on a comparison between said estimated delay and said predetermined amount of time, as a first target path, each said comparison is performed utilizing the same predetermined amount of time;

or

c′

) estimating wire lengths of interconnection lines included in each of the paths in accordance with the layout data, comparing said estimated wire lengths of said paths to a predetermined length, and selecting based on said comparison at least one of the paths which has an estimated wire length exceeding said predetermined length, as a second target path; and

d) extracting the parasitic elements from at least one of the graphic patterns, which correspond to the first or second target path.

8. A method for designing a semiconductor integrated circuit, which includes multiple circuit elements and multiple paths interconnecting those elements together, by extracting parasitic elements, associated with at least one of the paths, from the circuit to analyze operation timing of the circuit elements, the method comprising the steps of:

a) estimating delays, which will be caused by the respective paths, according to a netlist describing topology information about interconnections among the circuit elements;

b) forming graphic patterns for the multiple circuit elements and laying out the graphic patterns according to the netlist, thereby generating layout data;

c) selecting at least one of the paths, of which the estimated delay exceeds a predetermined amount of time based on a comparison between said estimated delay and said predetermined amount of time, as a first target path, each said comparison is performed utilizing the same predetermined amount of time;

or

c′

) estimating the length of pairs of interconnection lines, which are included in two adjacent ones of the paths and are substantially parallel to each other, comparing the estimated length of said pairs of interconnection lines to a predetermined length, and selecting based on said comparison at least two of the paths, in which the estimated length of the parallel interconnection lines exceeds said predetermined length, as target paths; and

d) extracting the parasitic elements from at least one of the graphic patterns, which correspond to the first target path or the second target paths.

9. The method of claim 8, wherein the step c′

) comprises the step of sorting out the least two paths, in which the estimated length of the parallel interconnection lines exceeds the predetermined length, as paths to be analyzed for crosstalk, and

wherein step d) comprises the step of extracting the parasitic elements from the graphic patterns corresponding to the paths to be analyzed for crosstalk.