Clock template for configuring a programmable gate array

• US 6,732,347 B1
• Filed: 04/26/2001
• Issued: 05/04/2004
• Est. Priority Date: 04/26/2001
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Kong, Raymond, Lindholm, Jeffrey V., McGettigan, Edward S., Bixler, Kevin L., Stickney, Kenneth J. Jr., Camilleri, Nicolas J.
• Primary Examiner(s): Thompson, A. M.
• Application Number:
  US09/844,054
• Time in Patent Office: 1,104 Days
• Field of Search: 716/16, 716/18, 716/3
• US Class Current: 716/117
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A clock template includes digital programming information for programming clock frames of a programmable gate array (PGA). The digital programming information represents a number of different clock configurations that correspond to various designs in the PGA. In one embodiment, the digital programming information includes a bit stream for partially reconfiguring the PGA. In another embodiment, the digital programming information is embedded in digital programming information of at least one of the designs. Methods of configuring a PGA with different designs having different clocking configurations by utilizing the clock template are also disclosed.

Claims

1. A clock template comprising digital programming information representative of a plurality of different clock configurations,

wherein the plurality of different clock configurations correspond to a plurality of designs for programming clock frames of a programmable gate array (PGA), and

wherein the digital programming information comprises information used to configure the PGA in accordance with said corresponding plurality of designs.

2. The clock template of claim 1 wherein the digital information comprises a bit stream for partially reconfiguring the PGA.

3. The clock template of claim 2 wherein the bit stream is produced from a compilation of a high level descriptive design language program of clock configuration extracts from a plurality of high level descriptive design language programs of the designs.

4. The clock template of claim 1 comprising extracts of clock configurations copied from the plurality of designs, said extracts being embedded in digital programming information of at least one of the plurality of designs.

5. The clock template of claim 4 comprising a bit stream produced from a compilation of a high level descriptive design language program of the at least one design embedding the clock configuration extracts.

6. The clock template of claim 1 wherein the digital information comprises a bit stream for partially reconfiguring the PGA, said bit stream comprising bit streams of clock configurations copied from bit streams compiled from the plurality of designs.

7. The clocking template of claim 1 comprising dummy logic in high level descriptive design language for the different clock configurations.

8. The clocking template of claim 1 comprising special constraints in high level descriptive design language for the different clock configurations.

9. Method A method of configuring a PGA with a plurality of different designs having different clocking configurations, said method comprising the steps of:

creating a high level descriptive design language representation of each of the plurality of designs, each said design representation including a clocking configuration portion;

copying said clocking configuration portions from said design representations into a high level descriptive design language clock template; and

using said clock template to configure the PGA.

10. The method of claim 9 including the steps of:

compiling the clock template as an independent high level descriptive design language file to produce a bit stream representation thereof; and

programming clocking frames of the PGA with said clock template bit stream representation.

11. The method of claim 10 wherein the step of programming includes partially reconfiguring the clocking frames of the PGA with said clock template bit stream representation.

12. The method of claim 9 including the steps of:

embedding the clock template into at least one of the high level descriptive language designs of the plurality to form at least one composite high level descriptive design language file;

compiling each said composite file as an independent high level descriptive design language file to produce a bit stream representation thereof; and

programming clocking frames of the PGA with one of said composite file bit stream representations.

13. The method of claim 12 wherein the step of programming includes configuring the PGA with said one composite file bit stream representation.

14. The method of claim 12 including the steps of:

compiling high level descriptive language files of designs of the PGA to produce partial bit stream design representations thereof, wherein said partial bit stream design representations do not include clock configurations; and

partially reconfiguring the PGA with said partial bit stream design representations.

15. The method of claim 12, wherein:

the step of compiling includes compiling each composite file as an independent high level descriptive design language file to produce at least one full bit stream representation and partial bit stream representations, wherein said partial bit stream representations do not include clock configurations; and

the step of programming includes configuring the PGA with the full bit stream representation of a designated composite file first, and then, partially reconfiguring the PGA with partial bit stream representations of designs other than the design of the designated composite file.

16. The method of claim 9 including the step of adding to the clock template dummy logic high level descriptive design language representations for the clocking configurations of the clock template.

17. The method of claim 9 including the step of adding to the clock template special constraints high level descriptive design language representations for the clocking configurations of the clock template.

18. A method of configuring a PGA with a plurality of different designs having different clocking configurations, said method comprising the steps of:

creating a high level descriptive design language representation of each of the plurality of designs, each said design representation including a clocking configuration portion;

compiling the design representations as independent high level descriptive design language files to produce bit stream representations thereof;

extracting from said bit stream design representations bit stream portions representative of the clocking configurations of each design; and

programming clocking frames of the PGA with said extracted bit stream portions.

19. The method of claim 18 wherein the step of programming including the steps of combining the extracted bit stream portions to form a clock template;

and configuring the clocking frames of the PGA with said clock template.

20. The method of claim 19 wherein the step of configuring includes partially reconfiguring the clocking frames of the PGA with the clock template.

21. The method of claim 18 wherein the step of programming includes partially reconfiguring the clocking frames of the PGA with the extracted bit stream portions.