Method for fabricating split gate flash memory cell

• US 6,734,066 B2
• Filed: 12/02/2002
• Issued: 05/11/2004
• Est. Priority Date: 05/24/2002
• Status: Expired due to Term

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Nanya Technology Corporation
• Inventors: Lee, Pei-Ing, Lin, Jeng-Ping, Lin, Chi-Hui, Lien, Jih-Chang
• Primary Examiner(s): Coleman, W. David
• Assistant Examiner(s): Kebede, Brook
• Application Number:
  US10/307,704
• Publication Number:
  US 20030218208A1
• Time in Patent Office: 526 Days
• Field of Search: 438/257-267, 438/243, 438/201, 257/314-320, 257/E29.129, 257/E29.3, 257/E21.179, 257/E21.422, 257/E21.68, 257/E21.681, 257/E21.685, 257/E21.687, 257/E21.688
• US Class Current: 438/259
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/23 with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A split gate flash memory cell. The memory cell includes a substrate, a conductive line, source/drain regions, an insulating layer, a conductive spacer, an insulating stud, a first conductive layer, and a first insulating spacer. The conductive line is disposed in a lower portion of the trench of the substrate. The source region is formed in the substrate adjacent to an upper portion of the conductive line having the insulating layer thereon. The conductive spacer is disposed on the upper sidewall of the trench serving as a floating gate. The insulating stud is disposed on the insulating layer. The first conductive layer is disposed over the substrate adjacent to the conductive spacer serving as a control gate. The first insulating spacer is disposed on the sidewall of the insulating stud to cover the first conductive layer. The drain region is formed in the substrate adjacent to the first conductive layer.

Claims

1. A method of fabricating a split gate flash memory cell, comprising:

providing a substrate having a trench;

forming a conductive insulated from the substrate in a lower portion of the trench serving as a source line;

forming a source region in the substrate adjacent to an upper portion of the conductive line;

forming an insulating layer on the conductive line;

forming a conductive spacer serving as a floating gate, protruding and insulated from the substrate on the upper sidewall of the trench;

forming an insulating stud on the insulating layer, with the top thereof higher than that of the conductive spacer in height;

forming a first conductive layer over the substrate adjacent to the conductive spacer, insulated from the conductive spacer and the substrate, respectively;

forming a first insulating spacer on the sidewall of the insulating stud to cover a part of the first conductive layer;

removing the first conductive layer using the first insulating spacer as a mask to expose the substrate, with the remaining first conductive layer used as a control gate; and

forming a drain region in the exposed substrate.

2. The method as claimed in claim 1, further comprising a step of forming a second conductive layer between the first conductive layer and the first insulating spacer.

3. The method as claimed in claim 2, wherein the second conductive layer is tungsten suicide.

4. The method as claimed in claim 1, wherein, after the step of forming the first insulating spacer, further forming a second insulating spacer on the sidewall of the first conductive layer.

5. The method as claimed in claim 4, wherein the second insulating spacer is silicon nitride.

6. The method as claimed in claim 4, further comprising the steps of:

forming a conductive plug on the drain region serving as a bit line contact;

forming a cap layer over the insulating stud and the first insulating spacer; and

forming a third conductive layer on the conductive plug and the cap layer serving as a bit line.

7. The method as claimed in claim 6, wherein the conductive plug is polysilicon.

8. The method as claimed in claim 6, wherein the cap layer is silicon oxide.

9. The method as claimed in claim 6, wherein the third conductive layer is tungsten.

10. The method as claimed in claim 1, wherein the conductive line polysilicon.

11. The method as claimed in claim 1, wherein the insulating layer is high density plasma oxide.

12. The method as claimed in claim 1, wherein the conductive spacer is doped polysilicon.

13. The method as claimed in claim 1, wherein the insulating stud is silicon oxide or boron silicate glass.

14. The method as claimed in claim 1, wherein the first conductive layer is doped polysilicon.

15. The method as claimed in claim 1, wherein the first insulating spacer is silicon nitride.

16. A method of fabricating a split gate flash memory cell, comprising:

providing a substrate covered by a first mask layer and a second mask layer in sequence, and a first opening formed in the first and second mask layers to expose the substrate;

etching the substrate under the first opening to form a trench in the substrate;

forming a conductive line insulated from the substrate in a lower portion of the trench serving as a source line;

forming a source region in the substrate adjacent to an upper portion of the conductive line;

etching the sidewall of the second mask layer to form a second opening having a step profile over the trench;

forming a first insulating layer on the conductive line;

forming a conformable first conductive layer on the second mask layer and the surface of the second opening and the trench;

filling the second opening and the trench with a sacrificial layer higher than the top of the first mask layer in height;

etching the first conductive layer using the sacrificial layer as a mask;

removing the sacrificial layer to expose the remaining first conductive layer;

etching the remaining first conductive layer to form a conductive spacer insulated from the substrate on the upper sidewall of the trench serving as a floating gate, wherein the conductive spacer covers the sidewall of the first mask layer;

filling the second opening with a second insulating layer lower than the top of the second mask layer in height;

removing the second mask layer to expose a part of the second insulating layer;

etching the sidewall of the exposed second insulating layer to form an insulating stud on the first insulating layer, the top of the insulating stud higher than that of the conductive spacer in height;

removing the first mask layer to expose the substrate;

forming a second conductive layer over the substrate adjacent to the conductive spacer, the second conductive layer insulated from the conductive spacer and the substrate, respectively;

forming a first insulating spacer on the sidewall of the insulating stud to cover a part of the second conductive layer;

removing the second conductive layer using the first insulating spacer as a mask to expose the substrate, with the remaining second conductive layer used as a control gate; and

forming a drain region in the exposed substrate.

17. The method as claimed in claim 16, further comprising forming a third conductive layer between the second conductive layer and the first insulating spacer.

18. The method as claimed in claim 17, wherein the third conductive layer is tungsten silicide.

19. The method as claimed in claim 16, wherein, after forming the first insulating spacer, further forming a second insulating spacer on the sidewall of the second conductive layer.

20. The memory cell as claimed in claim 19, wherein the second insulating spacer is silicon nitride.

21. The method as claimed in claim 19, further comprising the steps of:

forming a conductive plug on the drain region serving as a bit line contact;

forming a cap layer over the insulating stud and the first insulating spacer; and

forming a fourth conductive layer on the conductive plug and the cap layer serving as a bit line.

22. The method as claimed in claim 21, wherein the conductive plug is polysilicon.

23. The method as claimed in claim 21, wherein the cap layer is silicon oxide.

24. The method as claimed in claim 21, wherein the fourth conductive layer is tungsten.

25. The method as claimed in claim 16, wherein the first mask layer is composed of a pad oxide layer and a silicon nitride layer.

26. The method as claimed in claim 16, wherein the second mask layer is composed at a pad oxide layer and a silicon nitride layer.

27. The method as claimed in claim 16, wherein the conductive line is polysilicon.

28. The method as claimed in claim 16, wherein the first insulating layer is high density plasma oxide.

29. The method as claimed in claim 16, wherein the conductive spacer is doped polysilicon.

30. The method as claimed in claim 16, wherein the insulating stud is silicon oxide or boron silicate glass.

31. The method as claimed in claim 16, wherein the second conductive layer is doped polysilicon.

32. The method as claimed in claim 16, wherein the first insulating spacer is silicon nitride.

33. The method as claimed in claim 16, wherein the sacrificial layer is photoresist.