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Method for fabricating split gate flash memory cell

  • US 6,734,066 B2
  • Filed: 12/02/2002
  • Issued: 05/11/2004
  • Est. Priority Date: 05/24/2002
  • Status: Expired due to Term
First Claim
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1. A method of fabricating a split gate flash memory cell, comprising:

  • providing a substrate having a trench;

    forming a conductive insulated from the substrate in a lower portion of the trench serving as a source line;

    forming a source region in the substrate adjacent to an upper portion of the conductive line;

    forming an insulating layer on the conductive line;

    forming a conductive spacer serving as a floating gate, protruding and insulated from the substrate on the upper sidewall of the trench;

    forming an insulating stud on the insulating layer, with the top thereof higher than that of the conductive spacer in height;

    forming a first conductive layer over the substrate adjacent to the conductive spacer, insulated from the conductive spacer and the substrate, respectively;

    forming a first insulating spacer on the sidewall of the insulating stud to cover a part of the first conductive layer;

    removing the first conductive layer using the first insulating spacer as a mask to expose the substrate, with the remaining first conductive layer used as a control gate; and

    forming a drain region in the exposed substrate.

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