Method of making an edge seal for a semiconductor device

• US 6,734,090 B2
• Filed: 02/20/2002
• Issued: 05/11/2004
• Est. Priority Date: 02/20/2002
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Dalal, Hormazdyar Minocher, Liniger, Eric G., Engel, Brett H., Nguyen, Du Binh, Agarwala, Birendra N., Tian, Chunyan E., Llera-Hurlburt, Diana, Procter, Richard W., Rathore, Hazara Singh
• Primary Examiner(s): Gurley, Lynne
• Application Number:
  US10/078,861
• Publication Number:
  US 20030157794A1
• Time in Patent Office: 811 Days
• Field of Search: 438/637-639, 438/687, 438/121, 438/462, 438/597, 438/598, 438/599, 438/618, 438/620, 438/666-669, 438/672, 438/700, 438/702
• US Class Current: 438/598
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

An edge seal around the periphery of an integrated circuit device which environmentally protects the copper circuitry from cracks that may form in the low-k interlevel dielectric during dicing. The edge seal essentially constitutes a dielectric wall between the copper circuitry and the low-k interlevel dielectric near the periphery of the integrated circuit device. The dielectric wall is of a different material than the low-k interlevel dielectric.

Claims

1. A method of forming an edge seal along a periphery of an integrated circuit device to provide increased corrosion and oxidation resistance to metallization of the integrated circuit device, the method comprising the steps of:

a. providing a semiconductor substrate having a metallic feature therein;

b. depositing a layer of dielectric material over the semiconductor substrate and metallic feature, the layer of dielectric material comprising a low-k dielectric material;

c. selectively removing a portion of the layer of dielectric material to form a cavity and expose a portion of the metallic feature;

d. conformally depositing a layer of an insulation material in the cavity and over the layer of dielectric material, wherein the insulation material and dielectric material are different materials;

e. removing horizontal portions of the layer of insulation material so as to expose at least the metallic feature in the cavity;

f. depositing a barrier metal on the layer of insulation material in the cavity and on the exposed metallic feature;

g. depositing a high conductivity metal in the cavity to fill the cavity; and

h. planarizing the semiconductor substrate down to the layer of dielectric material to form said edge seal.

2. The method of claim 1 wherein the low-k dielectric material comprises SiLK or fluoridized polyimide.

3. The method of claim 1 wherein the layer of dielectric material comprises a bottom layer on the semiconductor substrate, the low-k dielectric material on the bottom layer and a top moisture barrier on the low-k dielectric material.

4. The method of claim 1 wherein the insulation material is selected from the group consisting of SiO₂, SiC, Si₃N4, Al₂O₃, diamond like carbon, polyimide and combinations thereof.

5. The method of claim 1 wherein the barrier layer is selected from the group consisting of tantalum, tantalum nitride, chromium/chromium oxide, titanium, titanium nitride, tungsten silicide and combinations thereof.

6. The method of claim 1 wherein the high conductivity metal is copper.

7. The method of claim 1 wherein the thickness of the insulation material in the cavity is 0.05 microns to 0.5 microns.

8. The method of claim 1 wherein the cavity comprises at least two contiguous cavities which form a damascene structure.

9. A method of forming an edge seal along a periphery of an integrated circuit device to provide increased corrosion and oxidation resistance to metallization of the integrated circuit device, the method comprising the steps of:

a. providing a semiconductor substrate having a metallic feature therein;

b. depositing a layer of dielectric material over the semiconductor substrate and metallic feature, the layer of dielectric material comprising a low-k dielectric material;

c. selectively removing a portion of the layer of dielectric material to form two first cavities and expose a portion of the metallic feature;

d. depositing an insulation material to fill the two first cavities, wherein the insulation material and dielectric material are different materials;

e. selectively removing a portion of the layer of dielectric material, and any overlying insulation material to form a second cavity and expose the metallic feature;

f. depositing a barrier metal in the second cavity and on the exposed metallic feature;

g. depositing a high conductivity metal in the second cavity to fill the cavity; and

h. planarizing the semiconductor substrate down to the layer of dielectric material to form said edge seal.