Insulated gate bipolar transistor, semiconductor device, method of manufacturing insulated-gate bipolar transistor, and method of manufacturing semiconductor device

• US 6,734,497 B2
• Filed: 09/27/2002
• Issued: 05/11/2004
• Est. Priority Date: 02/02/2001
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki, Tomomatsu, Yoshifumi, Tabata, Mitsuharu
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US10/239,212
• Publication Number:
  US 20030042575A1
• Time in Patent Office: 592 Days
• Field of Search: 257/565-612, 257/401, 257/341-345, 257/138-145, 438/309-328, 438/350
• US Class Current: 257/341
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48139 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01041 : Niobium [Nb]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H02M 7/003 : Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Abstract

An insulated gate bipolar transistor, a semiconductor device using such a transistor, and manufacturing methods of these. The transistor, device, and method eliminate the necessity of connection to a freewheel diode used for bypassing a circulating current. In the transistor, device, and method the concentration of impurities of an N+ buffer layer that forms a junction with a P+ collector layer is increased so that it is possible to reduce an avalanche breakdown voltage of a parasitic diode formed by an N base layer and the P+ collector layer. Thus, the reverse voltage resistance of an IGBT is lowered to not more than 5 times the collector-emitter saturated voltage.

Claims

1. An insulated gate bipolar transistor comprising:

a semiconductor substrate having first and second major surfaces;

a collector electrode which is located on said first major surface side of said semiconductor substrate; and

an emitter electrode and a gate electrode that are located on said second major surface side,

wherein said semiconductor substrate comprises;

a collector layer of a first conductive type that is exposed to said first major surface and connected to said collector electrode; and

a base layer of a second conductive type that is formed on said collector layer and is not exposed to said first major surface, and

wherein said base layer and said collector layer have a characteristic as a freewheel diode.

2. The insulated gate bipolar transistor according to claim 1,

wherein a reverse voltage resistance, which is a minimum value of a collector-emitter voltage when a reverse current flows between said emitter electrode and said collector electrode, is set to not more than 5 times a collector-emitter saturated voltage.

3. The insulated gate bipolar transistor according to claim 2,

wherein said base layer comprises:

a base main body portion; and

a buffer layer that has a higher concentration of impurities than said base main body portion and is interpolated between said collector layer and said base main body portion, and

a minimum value of a collector-emitter voltage when an avalanche current flows through a parasitic diode formed by said base layer and said collector layer is equivalent to said reverse voltage resistance.

4. The insulated gate bipolar transistor according to claim 2,

wherein said semiconductor substrate further comprises:

a reverse conductive-type layer of said second conductive type that is formed inside said collector layer so as not to be connected to said base layer, and selectively exposed to said first major surface, and connected to said collector electrode, and

a minimum value of a collector-emitter voltage, that causes a punch through in which a depletion layer generated in a PN junction between said base layer and said collector layer reaches said reverse conductive-type layer, is equivalent to said reverse voltage resistance.

5. The insulated gate bipolar transistor according to claim 4,

wherein said collector layer comprises:

a low impurity concentration collector layer; and

a high impurity concentration collector layer,

said low impurity concentration collector layer comprises a portion of said collector layer sandwiched by said base layer and said reverse conductive-type layer, and

said high impurity concentration collector layer has a concentration of impurities higher than said low impurity concentration collector layer.

6. The insulated gate bipolar transistor according to claim 2,

wherein said semiconductor substrate further comprises:

a reverse conductive-type layer of said second conductive type that is formed inside said collector layer so as not to be connected to said base layer, and selectively exposed to said first major surface and connected to said collector electrode, and

a minimum value of a collector-emitter voltage when a parasitic bipolar transistor formed by said base layer, said collector layer and said reverse conductive type layer turns on, is equivalent to said reverse voltage resistance.

7. The insulated gate bipolar transistor according to claim 6,

wherein said collector layer comprises:

a low impurity concentration collector layer; and

a high impurity concentration collector layer, and

said low impurity concentration collector layer comprises a portion of said collector layer sandwiched by said base layer and said reverse conductive-type layer, and

said high impurity concentration collector layer has a concentration of impurities higher than said low impurity concentration collector layer.

8. The insulated gate bipolar transistor according to claim 2,

wherein said reverse voltage resistance is not more than 10 V.

9. A semiconductor device comprising:

the insulated gate bipolar transistor according to claim 1;

a housing in which the insulated gate bipolar transistor is mounted; and

three terminals each of which is attached to said housing with its one portion protruding from said housing toward the exterior, and which are electrically connected to said gate electrode, said emitter electrode and said collector electrode of the insulated gate bipolar transistor, respectively.

10. The semiconductor device according to claim 9,

wherein said gate electrode, said emitter electrode and said collector electrode are electrically connected to said three terminals through conductive wires, respectively.

11. The semiconductor device according to claim 9, further comprising:

the insulated gate bipolar transistor serving as a first transistor;

three insulated gate bipolar transistors having the same structure as said first transistor and serving as second through fourth transistors;

said three-terminals serving as first to third terminals; and

five terminals each of which is attached to said housing with one portion thereof protruding from said housing toward the exterior, said five terminals serving as fourth to eighth terminals, wherein

said first and second transistors are series-connected,

said third and fourth transistors are series-connected,

said first terminal is electrically connected to said collector electrodes of said first and third transistors,

said second terminal is electrically connected to connecting sections of said first and second transistors,

said third terminal is electrically connected to said gate electrode of said first transistor,

said fourth terminal is electrically connected to said emitter electrodes of said second and fourth transistors,

said fifth terminal is electrically connected to connecting sections of said third and fourth transistors, and

said sixth through eighth terminals are electrically connected to said gate electrodes of said second through fourth transistors, respectively.

12. The semiconductor device according to claim 11, further comprising:

an inductive load connected to said second terminal and said fifth terminal.

13. A semiconductor device comprising:

the insulated gate bipolar transistor according to claim 1;

a sealing member that seals the insulated gate bipolar transistor; and

three terminals each of which is sealed by said sealing member with one portion thereof protruding from said sealing member toward the exterior, said three terminals electrically connected to said gate electrode, said emitter electrode and said collector electrode of the insulated gate bipolar transistor, respectively.

14. A manufacturing method of an insulated gate bipolar transistor which comprises a semiconductor substrate having first and second major surfaces, a collector electrode that is located on said first major surface side of said semiconductor substrate, and an emitter electrode and a gate electrode that are located on said second major surface side, comprising the steps of:

(a) forming said semiconductor substrate so as to provide a collector layer of a first conductive type that is exposed to said first major surface and a base layer of a second conductive type that is formed on said collector layer and is not exposed to said first major surface; and

(b) forming said collector electrode on said first major surface so as to be connected to said collector layer,

wherein in said step (a), said semiconductor substrate is formed so that said base layer and said collector layer are allowed to have a characteristic as a freewheel diode.

15. The manufacturing method of the insulated gate bipolar transistor according to claim 14, wherein

in said step (a), said semiconductor substrate is formed in such a manner that a reverse voltage resistance, which is a minimum value of a collector-emitter voltage when a reverse current flows between said emitter electrode and said collector electrode, is set to not more than 5 times the collector-emitter saturated voltage.

16. The manufacturing method of the insulated gate bipolar transistor according to claim 15, wherein

in said step (a), said base layer comprises a base main body portion and a buffer layer that has a higher concentration in impurities than said base main body portion and is interpolated between said collector layer and said base main body portion, and

said semiconductor substrate is formed so that a minimum value of a collector-emitter voltage when an avalanche current flows through a parasitic diode formed by said base layer and said collector layer is equivalent to said reverse voltage resistance.

17. The manufacturing method of the insulated gate bipolar transistor according to claim 15, wherein

in said step (a), said semiconductor substrate further comprises a reverse conductive-type layer of said second conductive type that is formed inside said collector layer so as not to be connected to said base layer, and selectively exposed to said first major surface, and connected to said collector electrode, and

said semiconductor substrate is formed so that a minimum value of a collector-emitter voltage that causes a punch through in which a depletion layer generated in a PN junction between said base layer and said collector layer reaches said reverse conductive-type layer is equivalent to said reverse voltage resistance.

18. The manufacturing method of the insulated gate bipolar transistor according to claim 15, wherein

in said step (a), said semiconductor substrate further comprises a reverse conductive-type layer of said second conductive type that is formed inside said collector layer so as not to be connected to said base layer, and selectively exposed to said first major surface, and connected to said collector electrode, and

said semiconductor substrate is formed so that a minimum value of a collector-emitter voltage when a parasitic bipolar transistor formed by said base layer, said collector layer and said reverse conductive type layer turns on is equivalent to said reverse voltage resistance.