Microelectronic substrate with integrated devices

• US 6,734,534 B1
• Filed: 10/19/2000
• Issued: 05/11/2004
• Est. Priority Date: 08/16/2000
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Li, Jian, Vu, Quat T., Towle, Steven
• Primary Examiner(s): Williams, Alexander O.
• Application Number:
  US09/692,908
• Time in Patent Office: 1,300 Days
• Field of Search: 257/782, 257/774, 257/680, 257/700, 257/701, 257/702, 257/703, 257/723, 257/685, 257/686, 257/690-693, 257/696, 257/698, 257/684, 257/796, 174/52.1, 174/52.2, 174/52.3, 174/52.4
• US Class Current: 257/668
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A microelectronic substrate including at least one microelectronic die disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic dice, or a plurality microelectronic dice encapsulated without the microelectronic substrate core. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

Claims

1. A microelectronic substrate, comprising:

a core having a first surface and an opposing second surface, the core having at least one opening defined therein extending from the core first surface to the core second surface;

at least one die disposed within the at least one opening, the at least one die having an active surface;

an encapsulation material adhering the core to the at least one die;

a first dielectric layer disposed above and on at least one of the core, the die, and the encapsulation material;

a first plurality of conductive traces disposed above and on the first dielectric layer;

a second dielectric layer including a second plurality of vias, disposed above and on the first dielectric layer and the first plurality of conductive traces;

a second plurality of conductive traces disposed above and on the second dielectric layer; and

a plurality of conductive-bumps disposed above an on the second plurality of conductive traces, wherein at least two of the first dielectric layer, the first plurality of conductive traces, the second dielectric layer, and the second plurality of conductive traces further include interconnection layers, the microelectronic substrate further including;

at least two microelectronic devices attached at the plurality of conductive bumps, wherein the at least two microelectronic devices include a variety of shapes and sizes.

4. The microelectronic substrate of claim 1, wherein each of the second plurality of conductive traces includes a landing pad.

2. A microelectronic substrate, comprising:

a core having a first surface and an opposing second surface, the core having at least one opening defined therein extending from the core first surface to the core second surface;

at least two dice disposed within the at least one opening, each of the at least two dice having an active surface;

an encapsulation material adhering the core to the at least two dice;

a first dielectric layer disposed above and on at least one of the core, the at least two dice, and the encapsulation material;

a first plurality of conductive traces disposed above and on the first dielectric layer;

a second dielectric layer including a second plurality of vias, disposed above and on the first dielectric layer and the first plurality of conductive traces; and

a second plurality of conductive traces disposed above and on the second dielectric layer, wherein at least two of the first dielectric layer, the first plurality of conductive traces, the second dielectric layer, and the second plurality of conductive traces further include interconnection layers, the microelectronic substrate further including;

at least two microelectronic devices attached at the plurality of conductive bumps, wherein the at least two microelectronic devices include a variety of shapes and sizes.

3. The microelectronic substrate of claim 2, wherein each of the second plurality of conductive traces includes a landing pad.