Post passivation interconnection schemes on top of the IC chips

• US 6,734,563 B2
• Filed: 10/22/2002
• Issued: 05/11/2004
• Est. Priority Date: 10/18/2000
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US10/278,106
• Publication Number:
  US 20030057531A1
• Time in Patent Office: 567 Days
• Field of Search: 257/700, 257/690, 257/691, 257/920, 257/773, 257/774, 438/614, 438/615, 438/616, 438/622
• US Class Current: 257/773
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Claims

1. A post passivation interconnect structure, comprising:

one or more internal circuits comprising one or more active devices formed in and on a semiconductor substrate;

one or more ESD circuits formed in and on said semiconductor substrate;

a fine line metallization system, formed over said semiconductor substrate in one or more thin layers of dielectric;

a passivation layer over said fine line metallization system;

a thick, wide metallization system formed above said passivation layer, in one or more thick layers of dielectric,

wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for an electrical stimulus, and wherein said thick, wide metallization system is connected to said one or more ESD circuits, said one or more internal circuits, and to at least one off-chip contact pin.

2. The interconnect structure of claim 1 wherein said distribution network is connected to said ESD circuits and to said one or more internal circuits by vias, which are formed through said one or more thick layers of dielectric, through said passivation layer, and through said one or more thin layers of dielectric.

3. The interconnect structure of claim 2 wherein said electrical stimulus comprises a power or ground voltage.

4. The interconnect structure of claim 3 wherein said ESD circuit is connected in parallel with said one or more internal circuits, through said distribution network.

5. The interconnect structure of claim 3 wherein said distribution network acts as a global distribution for said power or ground voltages, and said vias are further connected to local power/ground distribution networks formed in said fine line metallization system.

6. The interconnect structure of claim 2 wherein said electrical stimulus comprises a clock or signal voltage.

7. The interconnect structure of claim 6, further comprising driver, receiver or I/O circuits connected in series between said one or more off-chip contact pins and said distribution network.

8. The interconnect structure of claim 7 wherein said ESD circuit is connected in parallel with said driver, receiver or I/O circuits.

9. The interconnect structure of claim 6 wherein said distribution network acts as a global distribution for said clock or signal voltages, and said vias are further connected to local clock/signal distribution networks formed in said fine line metallization system.

10. The interconnect structure of claim 1 wherein metal in said thick, wide metallization system is greater than about 1 micrometer in thickness.

11. The interconnect structure of claim 1 wherein said one or more thick layers of dielectric are each greater than about 2 micrometers in thickness.

12. A post passivation interconnect structure, comprising:

one or more internal circuits comprising one or more active devices formed in and on a semiconductor substrate;

one or more ESD circuits formed in and on said semiconductor substrate;

a fine line metallization system, formed over said semiconductor substrate in one or more thin layers of dielectric;

a passivation layer over said fine line metallization system;

a thick, wide metallization system formed above said passivation layer, in one or more thick layers of dielectric,

wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a power or ground distribution network for a power or ground input, respectively, and wherein said thick, wide metallization system is connected to said one or more internal circuits, and to at least one off-chip contact pin.

13. The interconnect structure of claim 12 further comprising one or more ESD circuits, formed in and on said semiconductor substrate, connected to said distribution network, and in parallel with said one or more internal circuits.

14. The interconnect structure of claim 13 wherein said distribution network is connected to said ESD circuits and to said one or more internal circuits by vias, which are formed through said one or more thick layers of dielectric, through said passivation layer, and through said one or more thin layers of dielectric.

15. The interconnect structure of claim 12 wherein said distribution network acts as a global distribution for said power or ground inputs, and said vias are further connected to local power/ground distribution networks formed in said fine line metallization system.

16. The interconnect structure of claim 13 wherein there is one or more ESD circuit for each said off-chip contact pin.

17. The interconnect structure of claim 12 wherein metal in said thick, wide metallization system is greater than about 1 micrometer in thickness.

18. The interconnect structure of claim 12 wherein said one or more thick layers of dielectric are each greater than about 2 micrometers in thickness.

19. A post passivation interconnect structure, comprising:

one or more internal circuits comprising one or more active devices formed in and on a semiconductor substrate;

a fine line metallization system, formed over said semiconductor substrate in one or more thin layers of dielectric;

a passivation layer over said fine line metallization system;

a thick, wide metallization system formed above said passivation layer, in one or more thick layers of dielectric,

wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for a clock or signal voltage, and wherein said thick, wide metallization system is connected to said one or more internal circuits.

20. The interconnect structure of claim 19 wherein said distribution network is connected to said one or more internal circuits by vias, which are formed through said one or more thick layers of dielectric, through said passivation layer, and through said one or more thin layers of dielectric.

21. The interconnect structure of claim 20 wherein said distribution network acts as a global distribution for said clock or signal voltages, and said vias are further connected to local clock or signal distribution networks, respectively, formed in said fine line metallization system.

22. The interconnect structure of claim 19 wherein metal in said thick, wide metallization system is greater than about 1 micrometer in thickness.

23. The interconnect structure of claim 19 wherein said one or more thick layers of dielectric are each greater than about 2 micrometers in thickness.