Cache invalidation method and apparatus for a graphics processing system

• US 6,734,867 B1
• Filed: 06/28/2000
• Issued: 05/11/2004
• Est. Priority Date: 06/28/2000
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Peterson, James R., Munshi, Aaftab
• Primary Examiner(s): Bella, Matthew C.
• Assistant Examiner(s): Monestime, Mackly
• Application Number:
  US09/607,504
• Time in Patent Office: 1,413 Days
• Field of Search: 345/531, 345/532, 345/536, 345/537, 345/557, 345/558, 711/121, 711/118, 711/135, 711/136, 711/144, 711/158, 711/113
• US Class Current: 345/557
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means

Abstract

A cache for a graphics system storing both an address tag and an identification number for each block of data stored in the data cache. An address and identification number of a requested block of data is provided to the cache, and is checked against all of the address and identification number entries present. A block of data is provided if both the address and the identification number of the requested data matches an entry in the cache. However, if the address of the requested data is not present, or if the address matches an entry but the associated identification number does not match, a cache miss occurs, and the requested graphics data must be retrieved from a system memory. The address and identification number are updated, and the requested data replaces the former graphics data in the data cache. As a result, a block of data stored in the cache having the same address as the requested data, but having data that is invalid, can be invalidated without invalidating the entire cache.

Claims

1. A cache memory system for storing blocks of graphics data in a graphics processing system, the cache memory system comprising:

a first memory to store an address and an associated ID number for each block of graphics data stored in the cache memory, the address corresponding to a storage location in the cache memory and the associated ID number assigned to distinguish between blocks of graphics data having the same address;

a second memory to store blocks of graphics data corresponding to the addresses and associated ID numbers stored in the first memory; and

a cache controller coupled to the first and second memories, in response to receiving a requested address and ID number for graphics data matching one of the addresses and associated ID numbers stored in the first memory, the cache controller controlling the second memory to output the block of graphics data corresponding to the matching address and associated ID number, in response to a stored entry having an address tag matching the requested address but an associated ID number not matching the requested ID number, the cache controller retrieving from a third memory graphics data corresponding to the requested address and ID number, replacing in the first memory the associated ID number for the stored entry and the corresponding graphics data in the second memory with the retrieved graphics data, and controlling the second memory to output the retrieved graphics data.

2. The cache memory of claim 1 wherein the first memory comprises a tag cache to store the address of each block of graphics data and an ID cache to store the associated ID number.

3. The cache memory of claim 1 wherein the second memory comprises a data cache.

4. The cache memory of claim 1 wherein the associated ID number is assigned to the blocks of graphics data when written to the memory and corresponds to a frame number of a graphics frame in which the blocks of graphics data is first used for rendering.

5. The cache memory of claim 1, further comprising an invalidation circuit coupled to the first memory to reset the addresses and associated ID numbers in the first memory to a predetermined value.

6. A cache memory for storing graphics data in a graphics processing system, the cache memory comprising:

a first memory means for storing addresses corresponding to memory addresses at which the graphics data is stored;

a second memory means for storing an ID number associated with the graphics data for each address stored in the first memory means;

a data cache means for storing the graphics data corresponding to the addresses and ID numbers stored in the first and second memory means, respectively;

a cache controller means coupled to the first and second memory means and the data cache means, in response to receiving an address and ID number for requested graphics data matching an entry stored in the first and second memory means, respectively, the cache controller means generating a hit signal causing the data cache means to provide the graphics data corresponding to the matching address and ID number, in response to a stored entry having an address tag matching the requested address but an associated ID number not matching the requested ID number, the cache controller means retrieving from a third memory graphics data corresponding to the requested address and ID number, replacing in the second memory means the associated ID number for the stored entry and the corresponding graphics data in the data cache means with the retrieved graphics data, and causing the data cache means to provide the retrieved graphics data.

7. The cache memory of claim 6, further comprising an invalidation circuit coupled to the first memory to reset the addresses and associated ID numbers in the first memory to a predetermined value.

8. A computer system, comprising:

a central processing unit;

a system memory coupled to the CPU;

a bus coupled to the CPU; and

a graphics processing system coupled to the bus having a graphics processor assigning ID numbers to blocks of graphics data stored in the system memory and a graphics processing stage receiving a requested address and ID number for graphics data from the graphics processor, the graphics processing stage including a cache memory for storing blocks of graphics data written to the system memory, the cache memory comprising;

a first memory to store an address and an associated ID number for each block of graphics data stored in the cache memory, the address corresponding to a storage location in the system memory and the associated ID number assigned by the graphics processor to distinguish between blocks of graphics data having the same address;

a second memory to store blocks of graphics data corresponding to the addresses and associated ID numbers stored in the first memory; and

a cache controller coupled to the first and second memories, in response to receiving a requested address and ID number for graphics data matching one of the addresses and associated ID numbers stored in the first memory, the cache controller controlling the second memory to output the block of graphics data corresponding to the matching address and associated ID number, in response to a stored entry having an address tag matching the requested address but an associated ID number not matching the requested ID number, the cache controller retrieving from a third memory graphics data corresponding to the requested address and ID number, replacing in the first memory the associated ID number for the stored entry and the corresponding graphics data in the second memory with the retrieved graphics data, and controlling the second memory to output the retrieved graphics data.

9. The computer system of claim 8 wherein the first memory comprises a tag cache to store the address of each block of graphics data and an ID cache to store the associated ID number.

10. The computer system of claim 9 wherein the second memory comprises a data cache.

11. The computer system of claim 9, further comprising an invalidation circuit coupled to the first memory to reset the addresses and associated ID numbers in the first memory to a predetermined value.

12. The computer system of claim 9 wherein the associated ID number is assigned to the blocks of graphics data when written to the memory and corresponds to a frame number of a graphics frame in which the blocks of graphics data is first used for rendering.

13. A computer system, comprising:

a central processing unit;

a system memory coupled to the CPU;

a bus coupled to the CPU; and

a graphics processing system coupled to the bus having a graphics processor assigning ID numbers to blocks of graphics data stored in the system memory and a graphics processing stage receiving a requested address and ID number for graphics data from the graphics processor, the graphics processing stage including a cache memory for storing blocks of graphics data written to the system memory, the cache memory retrieving the cached graphics data by;

comparing the requested address and ID number to stored entries in a first memory having an address tag and associated ID number;

providing from a second memory graphics data corresponding to one of the stored entries having an address tag and an associated ID number matching the requested address and ID number;

retrieving from a third memory a retrieved graphics data corresponding to the requested address and ID number in response to a stored entry having an address tag matching the requested address but an associated ID number not matching the requested ID number;

replacing in the first memory the associated ID number for the stored entry and the corresponding graphics data in the second memory with the retrieved graphics data; and

providing from the second memory the retrieved graphics data.

14. The computer system of claim 13 wherein the ID number assigned to blocks of graphics data stored in the system memory comprises a value corresponding to a frame number for a graphics frame being rendered when the blocks of graphics data are written to the system memory.

15. A method of caching blocks of graphics data stored in a memory, comprising:

assigning an ID number to blocks of graphics data stored in the memory, the ID number distinguishing between blocks of graphics data presently and formerly stored in the memory;

storing a tag and an ID number for each cached block of graphics data;

comparing a requested tag and ID number to the stored tags and ID numbers;

providing the cached block of graphics data corresponding to the tag and ID number matching the requested tag and ID number;

retrieving graphics data corresponding to the requested address and ID number in response to a stored tag matching the requested tag but the ID number associated with the stored tag not matching the requested ID number;

replacing the ID number associated with the stored tag and replacing the corresponding graphics data with the retrieved graphics data; and

providing the retrieved graphics data.

16. The method of claim 15 wherein assigning the ID number to blocks of graphics data stored in the memory comprises assigning a value to the blocks of graphics data when written to the memory corresponding to a frame number for which the block of graphics data is first referenced.

17. The method of claim 15 wherein assigning the ID number to the blocks of graphics data stored in the memory comprises assigning a unique value to blocks of graphics data.

18. A method of retrieving graphics data from a cache, comprising:

comparing a requested address and ID number to stored entries in a first memory having an address tag and associated ID number;

providing from a second memory graphics data corresponding to one of the stored entries having an address tag and an associated ID number corresponding to the requested address and ID number;

retrieving from a third memory a retrieved graphics data corresponding to the requested address and ID number in response to a stored entry having an address tag matching the requested address but an associated ID number not matching the requested ID number;

replacing in the first memory the associated ID number for the stored entry and the corresponding graphics data in the second memory with the retrieved graphics data; and

providing from the second memory the retrieved graphics data.

19. A graphics processing system for a computer system having a system memory, the graphics processing system, comprising:

a graphics processor assigning ID numbers to blocks of graphics data stored in the system memory;

a graphics processing stage receiving a requested address and ID number for graphics data from the graphics processor, the graphics processing stage including a cache memory for storing blocks of graphics data written to the system memory, the cache memory retrieving the cached graphics data by;

comparing the requested address and ID number to stored entries in a first memory having an address tag and associated ID number;

providing from a second memory graphics data corresponding to one of the stored entries having an address tag and an associated ID number matching the requested address and ID number;

retrieving from a third memory a retrieved graphics data corresponding to the requested address and ID number in response to a stored entry having an address tag matching the requested address but an associated ID number not matching the requested ID number;

replacing in the first memory the associated ID number for the stored entry and the corresponding graphics data in the second memory with the retrieved graphics data; and

providing from the second memory the retrieved graphics data.

20. The graphics processing system of claim 19 wherein the ID number assigned to blocks of graphics data stored in the system memory comprises a value corresponding to a frame number for a graphics frame being rendered when the blocks of graphics data are written to the system memory.

21. The graphics processing system of claim 19 wherein the third memory comprises the system memory of the computer system.