Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays

• US 6,735,104 B2
• Filed: 05/16/2003
• Issued: 05/11/2004
• Est. Priority Date: 03/21/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): HO, HOAI V
• Application Number:
  US10/440,377
• Publication Number:
  US 20030202404A1
• Time in Patent Office: 361 Days
• Field of Search: 365/51, 365/53, 365/230.03, 365/230.06, 365/63
• US Class Current: 365/51
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Claims

1. A memory device comprising:

a plurality of memory arrays comprising a first memory array and a second memory array;

a first circuit structure disposed beneath the first memory array, wherein the first circuit structure comprises all of the circuits disposed beneath the first memory array; and

a second circuit structure, different from the first circuit structure, disposed beneath the second memory array, wherein the second circuit structure comprises all of the circuits disposed beneath the second memory array.

2. The memory device of claim 1, wherein the first circuit structure includes at least one row decoder circuit.

3. The memory device of claim 2, wherein the second circuit structure includes at least one column decoder circuit.

4. The memory device of claim 2, wherein the first circuit structure includes a second row decoder circuit.

5. The memory device of claim 1, wherein the second circuit structure includes at least one column decoder circuit.

6. The memory device of claim 5, wherein the first circuit structure includes at least one row decoder circuit.

7. The memory device of claim 5, wherein the second circuit structure includes a second column decoder circuit.

8. The memory device of claim 1, wherein the plurality of memory arrays comprise first and second sets of memory arrays, wherein the first circuit structure is disposed beneath each of the memory arrays in the first set, and wherein the second circuit structure is disposed beneath each of the memory arrays in the second set.

9. A memory device comprising:

a plurality of memory arrays disposed above a substrate;

a first decoder circuit associated with and largely disposed beneath a first memory array and also associated with a second memory array; and

a second decoder circuit.

10. The memory device of claim 9, wherein the second memory array is adjacent to the first memory array.

11. The memory device of claim 9, wherein the second decoder circuit is associated with and largely disposed beneath the first memory array and is also associated with a third memory array.

12. The memory device of claim 11, wherein the third memory array is adjacent to the first memory array.

13. The memory device of claim 9 further comprising a third decoder circuit associated with and largely disposed beneath a fourth memory array, said third decoder circuit also associated with the first memory array.

14. The memory device of claim 13, wherein the fourth memory array is adjacent to the first memory array.

15. The memory device of claim 13 further comprising a fourth decoder circuit associated with and largely disposed beneath a fifth memory array, said fourth decoder circuit also associated with the first memory array.

16. The memory device of claim 15, wherein the fifth memory array is adjacent to the first memory array.

17. The memory device of claim 9 further comprising a group of array line driver circuits associated with the first decoder circuit, said group associated with the first memory array and the second memory array.

18. The memory device of claim 9 further comprising two groups of array line driver circuits associated with the first decoder circuit, one such group associated with the first memory array and the other such group associated with the second memory array.

19. The memory device of claim 9, wherein the first decoder circuit comprises a column decoder circuit.

20. The memory device of claim 9, wherein the first decoder circuit comprises a row decoder circuit.

21. The memory device of claim 20, wherein the row decoder circuit further comprises a first group of word line driver circuits associated with word lines within the first memory array and a second group of word line driver circuits associated with word lines within the second memory array, whereby word lines are discontinuous between the first and second memory arrays.

22. The memory device of claim 9 further comprising an additional plurality of memory arrays vertically-stacked above the first-mentioned plurality of memory arrays.

23. The memory device of claim 11 wherein the first memory array comprises first and second sets of array lines of like kind, wherein the first set of array lines is associated with the first decoder circuit and the second set of array lines is associated with the second decoder circuit, and wherein the array lines of the first set are interleaved with the array lines of the second set.

24. The memory device of claim 23 wherein the first set of array lines and the second set of array lines are driven from opposites sides of the first memory array.

25. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein at least one of the plurality of row or column decoder circuits is associated with a memory array above its location and an adjacent memory array.

26. The memory device of claim 25, wherein at least one of the plurality of row decoder circuits is associated with a memory array above its location and an adjacent memory array;

and further comprising only one set of word line drivers between adjacent memory arrays, whereby word lines are continuous between said adjacent memory arrays.

27. The memory device of claim 25, wherein at least one of the plurality of row decoder circuits is associated with a memory array above its location and an adjacent memory array;

and further comprising two sets of word line drivers between adjacent memory arrays, whereby word lines are not continuous between said adjacent memory arrays.

28. The memory device of claim 25, wherein at least one of the plurality of column decoder circuits is associated with a memory array above its location and an adjacent memory array;

and further comprising only one set of bit line drivers between adjacent memory arrays, whereby bit lines are continuous between said adjacent memory arrays.

29. The memory device of claim 25, wherein at least one of the plurality of column decoder circuits is associated with a memory array above its location and an adjacent memory array;

and further comprising two sets of bit line drivers between adjacent memory arrays, whereby bit lines are not continuous between said adjacent memory arrays.

30. The memory device of claim 25, wherein at least one row decoder circuit comprises a plurality of word line decoders, and wherein at least one word line decoder is connected to control an associated plurality of word lines.

31. The memory device of claim 30 wherein said at least one word line decoder is coupled to an associated plurality of word line drivers.

32. The memory device of claim 31 wherein each word line driver comprises a switch device arranged to couple the respective word line to an associated bias line.

33. The memory device of claim 31 wherein each word line driver comprises two devices arranged to couple the respective word line to either of two associated bias lines.

34. The memory device of claim 25 further comprising an additional plurality of memory arrays vertically-stacked above the first-mentioned plurality of memory arrays.

35. The memory device of claim 25 wherein a first memory array of said plurality of memory arrays comprises first and second sets of array lines of like kind, wherein the first set of array lines is associated with a first decoder circuit, and the second set of array lines is associated with a second decoder circuit, and wherein the array lines of the first set are interleaved with the array lines of the second set.

36. The memory device of claim 35 wherein the first set of array lines and the second set of array lines are driven from opposites sides of the first memory array.

37. The memory device of claim 35 wherein the first decoder circuit and the second decoder circuit are disposed beneath the first memory array.

38. The memory device of claim 25, wherein the plurality of memory arrays comprise a plurality of semiconductor-based memory cells.

39. The memory device of claim 25, wherein the plurality of memory arrays comprise a plurality of anti-fuse memory cells.

40. The memory device of claim 25, wherein the plurality of memory arrays comprise a plurality of write-once memory cells.

41. The memory device of claim 25, wherein the plurality of memory arrays comprise memory cells formed at least in part by railstacks.

42. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that any given memory array is either above a row decoder circuit or a column decoder circuit, but not both;

wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.

43. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that under any two adjacent memory arrays, there is exactly one row decoder circuit and exactly one column decoder circuit;

wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.

44. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for two adjacent memory arrays, there is a row decoder circuit but not a column decoder circuit under one of the two adjacent memory arrays and there is a column decoder circuit but not a row decoder circuit under the other of the two adjacent memory arrays;

wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.

45. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein a row decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one row decoder circuit, there is a column decoder circuit on each of the four sides;

wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.

46. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein a column decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one column decoder circuit, there is a row decoder circuit on each of the four sides;

wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.

47. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that any given memory array is either above a row decoder circuit or a column decoder circuit, but not both;

wherein the memory cells of the plurality of memory arrays comprise one of the following;

a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.

48. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that under any two adjacent memory arrays, there is exactly one row decoder circuit and exactly one column decoder circuit;

wherein the memory cells of the plurality of memory arrays comprise one of the following;

a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.

49. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for two adjacent memory arrays, there is a row decoder circuit but not a column decoder circuit under one of the two adjacent memory arrays and there is a column decoder circuit but not a row decoder circuit under the other of the two adjacent memory arrays;

wherein the memory cells of the plurality of memory arrays comprise one of the following;

a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.

50. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein a row decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one row decoder circuit, there is a column decoder circuit on each of the four sides;

wherein the memory cells of the plurality of memory arrays comprise one of the following;

a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.

51. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein a column decoder circuit defines four sides, and wherein the row decoder circuits and the column decoder circuits are arranged under the plurality of memory arrays such that for at least one column decoder circuit, there is a row decoder circuit on each of the four sides;

wherein the memory cells of the plurality of memory arrays comprise one of the following;

a semiconductor material, an organic polymer, a phase change material, and an amorphous solid.