High density dual bit flash memory cell with non planar structure

• US 6,735,123 B1
• Filed: 06/07/2002
• Issued: 05/11/2004
• Est. Priority Date: 06/07/2002
• Status: Expired due to Fees

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ramsbey, Mark T., Zheng, Wei, Ibok, Effiong, Cheung, Fred T K, Tripsas, Nicholas H.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/164,895
• Time in Patent Office: 704 Days
• Field of Search: 365/185.15, 365/185.26, 365/185.28, 257/324, 257/325, 257/411, 438/287, 438/981
• US Class Current: 365/185.26
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

A dual bit dielectric memory cell comprises a substrate with a source region and a drain region implanted on opposing sides of a central channel region. A multilevel charge trapping dielectric is positioned on the substrate above the central channel region and includes a central region between an opposing source lateral region and a drain lateral region. A control gate is positioned above the multilevel charge trapping dielectric. The multilevel charge trapping dielectric comprises a tunnel dielectric layer adjacent the substrate, a top dielectric adjacent the control gate, and a charge trapping dielectric positioned there between. The thickness of the tunnel dielectric layer in the central region is greater than a thickness of the tunnel dielectric layer in each of the source lateral region and the drain lateral region.

Claims

1. A method of storing data in dual bit dielectric memory cell that includes a tunnel dielectric layer having a tunnel dielectric layer with a thickness in a central region positioned between a source lateral region and a drain lateral region that is greater than a thickness in each of the source lateral region and the drain lateral region, and a continuous charge trapping layer overlying the tunnel dielectric layer, the method comprising:

a) utilizing a source-to-drain bias in the presence of a control gate field to induce hot electron injection through a tunnel dielectric thickness greater than the thickness in the source lateral region and less than the thickness in the central region to inject a charge into a source charge trapping region within the charge trapping layer; and

b) utilizing a drain-to-source bias in the presence of a control gate field to induce hot electron injection through a tunnel dielectric thickness greater than the thickness in the drain lateral region and less than the thickness in the central region to inject a charge into a drain charge trapping region within the charge trapping layer.

2. The method of claim 1, wherein the step of utilizing a source-to-drain bias in the presence of a control gate field to inject a charge into a source charge trapping region includes injecting a charge into a source charge trapping region comprising a nitride compound, and the step of utilizing a drain-to-source bias in the presence of a control gate field to inject a charge into a drain charge trapping region includes injecting a charge into a drain charge trapping region comprising the nitride compound.

3. The method of claim 2, wherein the step of utilizing a source-to-drain bias in the presence of a control gate field to inject a charge into a source charge trapping region includes injecting a charge into a source charge trapping region comprising a material selected from the group consisting of Si₃N₄ and SiO_xN₄, and the step of utilizing a drain-to-source bias in the presence of a control gate field to inject a charge into a drain charge trapping region includes injecting a charge into a drain charge trapping region comprising the material.

4. The method of claim 3, wherein the step of utilizing a source-to-drain bias in the presence of a control gate field to inject a charge into a source charge trapping region includes injecting a charge into a source charge trapping region that extends from about 300 Å

to about 500 Å

over a central channel region, and the step of utilizing a drain-to-source bias in the presence of a control gate field to inject a charge into a drain charge trapping region includes injecting a charge into a drain charge trapping region that extends from about 300 Å

to about 500 Å

over the central channel region.

5. A method of storing data in dual bit dielectric memory cell that includes a tunnel dielectric layer having a tunnel dielectric layer with a thickness in a central region positioned between a source lateral region and a drain lateral region that is greater then a thickness in each of the source lateral region and the drain lateral region, the method comprising:

a) utilizing a source-to-drain bias in the presence of a control gate field to induce hot electron injection through a tunnel dielectric thickness greater than the thickness in the source lateral region and less than the thickness in the central region to inject a charge into a source charge trapping region; and

b) utilizing a drain-to-source bias in the presence of a control date field to induce hot electron injection through a tunnel dielectric thickness greater than the thickness in the drain lateral region and less than the thickness in the central region to inject a charge into a drain charge trapping region,

wherein the step of utilizing a source-to-drain bias in the presence of a control gate field to inject a charge into a source charge trapping region includes injecting a charge into a source charge trapping region comprising a nitride compound, and the step of utilizing a drain-to-source bias in the presence of a control gate field to inject a charge into a drain charge trapping region includes injecting a charge into a drain charge-trapping region comprising the nitride compound.

6. The method of claim 5, wherein the step of utilizing a source-to-drain bias in the presence of a control gate field to inject a charge into a source charge trapping region includes injecting a charge into a source charge trapping region comprising a material selected from the group consisting of Si₃N₄ and SiO_xN₄, and the step of utilizing a drain-to-source bias in the presence of a control gate field to inject a charge into a drain charge trapping region includes injecting a charge into a drain charge trapping region comprising the material.

7. The method of claim 6, wherein the step of utilizing a source-to-drain bias in the presence of a control gate field to inject a charge into a source charge trapping region includes injecting a charge into a source charge trapping region that extends from about 300 Å

to about 500 Å

over a central channel region, and the step of utilizing a drain-to-source bias in the presence of a control gate field to inject a charge into a drain charge trapping region includes injecting a charge into a drain charge trapping region that extends from about 300 Å

to about 500 Å

over the central channel region.