Moderate rate phase shift keying codec

• US 6,735,258 B1
• Filed: 09/29/2000
• Issued: 05/11/2004
• Est. Priority Date: 09/29/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: ArrayComm LLC (Ygomi LLC)
• Inventors: Trott, Mitchell D., Boros, Tibor
• Primary Examiner(s): Tran, Khai
• Application Number:
  US09/675,910
• Time in Patent Office: 1,320 Days
• Field of Search: 375/308, 375/329, 375/279, 375/295, 375/316, 375/341, 375/269, 714/794, 714/795
• US Class Current: 375/308
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/0068 by puncturing
• CPC Class Codes: H04L 1/007 Unequal error protection for format H04L1/0078; for codes per se H03M13/35
• CPC Class Codes: H04L 1/06 using space diversity
• CPC Class Codes: H04L 27/18 Phase-modulated carrier systems, i.e. using phase-shift keying H04L27/32 takes precedence

Abstract

A method and apparatus are provided that yields bandwidth efficient low bit rate communication of digital signals in a noisy channel. According to one aspect of the present invention, the invention includes demultiplexing a received input bit stream to divide it into a first block and a second block, convolutionally coding the first block, block coding the second block, mapping the convolutionally coded first block to a sequence of three-bit symbols, so that the bits of the convolutionally coded first block make up one bit of each three-bit symbol, mapping the block coded bits of the second block to the sequence of three-bit symbols, so that the bits of the block coded second block make up two bits of the three-bit symbol, and mapping the three-bit symbols to a phase shift keyed constellation.

Claims

1. A method comprising:

demultiplexing a bit stream into a first block and a second block;

convolutionally coding the first block;

block coding the second block;

mapping the convolutionally coded first block to a sequence of three-bit symbols, the bits of the convolutionally coded first block making up one bit of each three-bit symbol;

mapping the block coded second block to the sequence of three-bit symbols, the bits of the block coded second block making up two bits of each three-bit symbol; and

mapping the three-bit symbols to a phase shift keyed constellation.

2. The method of claim 1, wherein demultiplexing the bit stream comprises placing a first successive portion of the stream into the first block and a second successive portion of the stream into the second block, so that the first block has approximately one fourth as many bits as the second block.

3. The method of claim 1, wherein convolutionally coding the first block comprises applying a 1 message bit per 2 coded bits convolutional coder.

4. The method of claim 1, wherein convolutionally coding comprises applying a coder with at least 128 states and a constraint length of at least eight.

5. The method of claim 1, wherein mapping the coded bits to a sequence of three-bit symbols comprises mapping the convolutionally coded bits to the least significant bit of each symbol.

6. The method of claim 1, wherein block coding the second block comprises adding a Hamming code to the second block.

7. The method of claim 1, wherein mapping the block coded bits to the three-bit symbols comprises mapping the block coded bits to the most significant bits of the three-bit symbols.

8. The method of claim 1, wherein mapping the three-bit symbols to a phase shift keyed constellation comprises mapping the three-bit symbols to an 8 PSK constellation.

9. The method of claim 1, further comprising puncturing the convolutionally coded bits of the first block before mapping.

10. An apparatus comprising:

a demultiplexer to divide an incoming bit stream into a first block and a second block;

a convolutional coder coupled to the demultiplexer to receive and code the first block;

a block coder coupled to the demultiplexer to receive and code the second block;

a first mapper to divide the coded second block into two blocks; and

a second mapper to map the coded first block and the two blocks of the coded second block to a sequence of three-bit symbols in a phase shift keyed constellation.

11. The apparatus of claim 10, wherein the convolutional coder comprises a 1 message bit per 2 coded bits convolutional coder.

12. The apparatus of claim 10, wherein the convolutional coder comprises a coder with at least 128 states and a constraint length of at least five.

13. The apparatus of claim 10, wherein the block coder comprises a Hamming code block coder.

14. The apparatus of claim 10, wherein the phase shift keyed constellation comprises an 8 PSK constellation.

15. A machine-readable medium having stored thereon data representing sequences of instructions which, when executed by a machine, cause the machine to perform operations comprising:

demultiplexing a bit stream into a first block and a second block;

convolutionally coding the first block;

block coding the second block;

mapping the convolutionally coded first block to a sequence of three-bit symbols, the bits of the convolutionally coded first block making up one bit of each three-bit symbol;

mapping the block coded second block to the sequence of three-bit symbols, the bits of the block coded second block making up two bits of each three-bit symbol; and

mapping the three-bit symbols to a phase shift keyed constellation.

16. The medium of claim 15, wherein the instructions for demultiplexing the bit stream comprise instructions causing the machine to perform operations comprising placing a first successive portion of the stream into the first block and a second successive portion of the stream into the second block, so that the first block has approximately one fourth as many bits as the second block.

17. The medium of claim 15, wherein the instructions for convolutionally coding the first block comprise instructions causing the machine to perform operations comprising applying a 1 message bit per 2 coded bits convolutional coder.

18. The medium of claim 15, wherein the instructions for mapping the coded bits to a sequence of three-bit symbols comprise instructions causing the machine to perform operations comprising mapping the convolutionally coded bits to the least significant bit of each symbol.

19. The medium of claim 15, wherein the instructions for block coding the second block comprise instructions causing the machine to perform operations comprising adding a Hamming code to the second block.

20. An apparatus comprising:

means for demultiplexing a bit stream into a first block and a second block;

means for convolutionally coding the first block;

means for block coding the second block;

means for mapping the convolutionally coded first block to a sequence of three-bit symbols, the bits of the convolutionally coded first block making up one bit of each three-bit symbol;

means for mapping the block coded second block to the sequence of three-bit symbols, the bits of the block coded second block making up two bits of each three-bit symbol; and

means for mapping the three-bit symbols to a phase shift keyed constellation.

21. The apparatus of claim 20, wherein the means for demultiplexing the bit stream comprises means for placing a first successive portion of the stream into the first block and a second successive portion of the stream into the second block, so that the first block has approximately one fourth as many bits as the second block.

22. The method of claim 20, wherein the means for block coding the second block comprises means for adding a Hamming code to the second block.

23. The method of claim 20, wherein the means for mapping the three-bit symbols to a phase shift keyed constellation comprises means for mapping the three-bit symbols to an 8 PSK constellation.