Digital coherent envelope demodulation of FDMA signals

• US 6,735,263 B1
• Filed: 05/22/2000
• Issued: 05/11/2004
• Est. Priority Date: 09/30/1999
• Status: Expired due to Fees

• Current Assignee: Mineral Lassen LLC (Intellectual Ventures LLC)
• Original Assignee: Netmor Ltd.
• Inventors: Itzkovitch, Moti, Albeck, Yehuda, Moriya, Netzer
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US09/575,517
• Time in Patent Office: 1,450 Days
• Field of Search: 375/326, 375/316, 375/260, 375/376, 370/208, 370/344, 370/319, 329/306, 329/307
• US Class Current: 375/326
• CPC Class Codes: G01S 3/043 Receivers
• CPC Class Codes: H04L 5/06 the signals being represented by different frequencies combined with time-division multiplexing H04L5/26

Abstract

A method for coherent detection and demodulation of a FDMA signal, that is a superposition of amplitude modulated carriers, is provided. An array of special digital phase-locked loops (PLLs) is implemented in a digital signal processor (DSP) for processing the received signal after it is digitized, and for extracting the envelopes corresponding to each carrier. Each PLL is deliberately made to slowly respond to error signals in order to allow the loop to preserve its phase while the amplitude value of the envelope flips sign. A down-decimation technique is employed in order to reduce the computational load. This is achieved by applying a finite impulse-response filter (FIR) only once per each frame, thereby only a single multiplication of the frame by the vector of filter'"'"'s taps is employed. A digital generation of sine and cosine sampled waveforms is employed inside a PLL by using a real-time solution of a difference equation. Implementation of the sine and cosine generation inside a PLL provides an automatic control of the sine and cosine phase.

Claims

1. A system for coherent detection and demodulation of a FDMA signal being a superposition of amplitude modulated carriers, the system comprising a digital coherent detector for receiving said FDMA electromagnetic signal, processing the signal and extracting a signed envelope of at least one amplitude modulated carrier, the detector comprising:

(i) a transducer for transforming said FDMA signal into analog electric signal;

(ii) a front-end electronics for receiving said analog electric signal and providing pre-amplification and pre-filtering of the input signal;

(iii) an analog to digital converter (ADC) for translating the electric signal coming after said front-end electronics into digitized signal data sampled at fixed ADC sampling intervals; and

(iv) a digital signal processor (DSP) for processing the digitized signal data and providing a real-time estimate of the signed envelope of at least one amplitude modulated carrier, the system synchronized by a synchronization signal delivering initial phase information to the DSP for estimation of the envelope sign.

2. The system of claim 1 wherein the detector further comprising an automatic gain control unit (AGC) integrated into the front-end electronics, the AGC is operative for keeping dynamic range of the data large enough to make optimal use of the digital depth provided by the ADC and keeping dynamic range of the data small enough to avoid an overflow of the ADC.

3. The system of claim 1 further comprising a synchronization-decoding unit having an input terminal coupled to said synchronization signal and an output terminal coupled to said digital coherent detector, said synchronization-decoding unit for comparing phase information delivered by the synchronization signal to the phase of the carrier as estimated by the said digital coherent detector, said estimate of the phase of the carrier is added half a cycle if the comparison yields a difference close to half a cycle between the said estimate of the phase of the carrier and said phase information delivered by the synchronization signal.

10. The system of claim 1 wherein the FDMA signal is electromagnetic signal.

4. The system of claim I wherein the DSP comprising:

(a) a framing unit for receiving the sampled digital data from the ADC and storing it in a DSP memory in a form of ready-to-process frames, each of the frames provides one point of the envelope;

(b) a shaping unit coupled to said framing unit for translating the data into a form readable by the DSP; and

(c) an at least one phase-locked loop unit (PLL) for receiving said frames of the data from the shaping unit, rejecting envelopes and carriers others than the one of interest and estimating the single envelope of the single carrier related to a specific source.

5. The system of claim 4 wherein the PLL comprising:

(a) a sine-wave multiplier and a cosine-wave multiplier for generating sine and cosine waves and down-converting the signal data provided by the shaping unit from the carrier frequency into the baseband by multiplication of said sine and cosine waves on said signal data;

(b) a digital, finite impulse-response (FIR), flat pass-band, and sharp cutoff low-pass filter (LPF) for receiving an input data signal and producing a filtered input data signal;

(c) a multiplier for multiplying only once per each frame said frame delivered from the shaping unit by a vector comprising the taps fo the LPF, whereby down-decimation of the data signal is obtained;

(d) a first multiply and accumulate unit (MAC-1) for summing the results of multiplication provided by the sine-wave multiplier referred to in element (a) and the multiplier defined in element (c);

(e) a second multiply and accumulate unit (MAC-2) for summing the results of multiplication provided by said cosine-wave multiplier and said multiplier;

(f) a phase detector for detecting the possible discrepancies between the frequencies and phases of the carrier and the sine-wave multiplier; and

for producing an error signal term δ

ω

for correcting the frequency and phase discrepancy; and

(g) an envelope computation unit for receiving the output of the MAC-1 and MAC-2 and computing the envelope.

6. The system of claim 5 wherein the phase detector comprising:

(a) a divider for dividing the output of the MAC-2 by the output of the MAC-1;

(b) a unit for computing an inverse tangent of the result provided by said divider;

(c) a loop filter wherein the output of said unit is split into two channels, the first channel comprising;

(i) a first gain unit for multiplication in the first channel the output of said unit by a constant K₁;

(ii) an integrator for integrating an output of the first gain unit over time, the second channel comprising a second gain unit for multiplication in the first channel the output of said unit by a constant K₂;

(d) an adder for summing outputs of said first and second channels.

7. The system of claim 6 wherein the constants K₁ and K₂ have values sufficient for preserving the phase of said sine-wave multiplier and cosine-wave multiplier, whereby sign preserving of the envelope is achieved.

8. The system of claim 5 wherein the envelope computation unit comprising:

(a) a first squaring operator for squaring the output of the MAC-1;

(b) a second squaring operator for squaring the output of the MAC-2;

(c) an adder of the envelope computation unit for summing outputs of the first squaring operator and the second squaring operator; and

(d) a square root operator for computing the square root of the summation provided by said adder.

9. The system of claim 5 wherein the sine-wave multiplier comprising:

(a) a sine computation unit for computing the term 2cos(ω

T_s+δ

ω

T_s), wherein ω

is the phase increment, T_s is the sampling interval of the ADC, and δ

ω

is the error signal term for correcting the frequency and phase discrepancy;

(b) a sine array for storing an output of the sine-waveform S_k of the k-th sample;

(c) a first delay unit for receiving the output of the sine array and producing a time delayed data signal S<sub>k−

1</sub>;

(d) a multiplier for multiplication of the delayed data signal S<sub>k−

1</sub> by the output of the sine computation unit;

(e) a second delay unit for receiving the output of the first delay unit and producing a double time delayed data signal S<sub>k−

2</sub>; and

(f) an adder for summing a negative value of the double time delayed data signal S<sub>k−

2</sub> and the output of said multiplier of item (d).

11. A method for coherent detection and demodulation of a FDMA signal being a superposition of amplitude modulated carriers of said transmitters, the method comprising the steps of:

(a) transforming the received FDMA signal into an analog electric signal by the transducer;

(b) providing pre-amplification and pre-filtering of the analog electric signal by a front-end electronics;

(c) translating the analog electric signal obtained after step b into digitized signal data sampled at fixed sampling intervals by an analog to digital converter (ADC);

(d) processing the digitized signal data obtained after step c by a digital signal processor (DSP);

(e) delivering phase information obtained after step (d) to the DSP and estimating an envelope by a synchronization signal, and

(f) providing a signed envelope of at least one amplitude modulated carrier.

12. The method of claim 11 wherein the step of processing the digitized signal data by the digital signal processor comprising the following steps:

(a) receiving the sampled digital data from the ADC and storing it in a DSP memory in a form of ready-to-process frames by a framing unit;

(b) translating the data into a form readable by the DSP by a shaping unit; and

(c) receiving frames of the data from the shaping unit, rejecting envelopes and carriers others than the one of interest and estimating the single envelope of the single carrier related to a specific transmitter by a phase-locked loop unit (PLL).

13. The method of claim 12 wherein the step of receiving frames, rejecting envelopes and carriers others than the one of interest and estimating the single envelope of the single carrier by the phase-locked loop unit (PLL) comprising the following steps:

(a) multiplying once per frame the frame delivered from the shaping unit by a vector of the taps of a low-pass filter by using a down-decimation technique, whereby multiplication of the frame by filter taps is performed only once per frame;

(b) generating sine and cosine waveforms;

(c) multiplying point-by-point the resulting frame of step (a) by a sine-wave, whereby down-conversion of the carrier is obtained, and summing the results by a first multiply and accumulate unit (MAC-1);

(d) multiplying point-by-point the resulting frame of step (a) by a cosine-wave, whereby down-conversion of the carrier is obtained, and summing the results by a second multiply and accumulate unit (MAC-2);

(e) feeding the results provided by the MAC-1 and MAC-2 into an envelop computation unit and into a phase detector;

(f) detecting the possible discrepancies between frequencies and phases of the carrier and the sine-wave and producing the error signal δ

ω

;

(g) feeding the error signal into sine and cosine multipliers; and

(h) computing the envelope and producing a demodulated signal from an output terminal of the envelope computing unit for as many frames as required until said envelope have been determined.

14. The method of claim 13 wherein the step of computing the envelope by the envelope computing unit comprising the following steps:

(a) squaring the output of the MAC-1 by the first squaring operator;

(b) squaring the output of the MAC-2 the second squaring operator;

(c) summing outputs of the first squaring operator and the second squaring operator; and

(d) computing the square root of the result of step (c), whereby said envelope of the carrier of interest will be calculated.

15. The method of claim 13 further comprising a step of assigning a sign to the envelope, wherein the assigned sign is the sign of the MAC-1.

16. The method of claim 13 wherein the step of detecting the possible discrepancies between frequencies and phases of the carrier and the sine-wave and producing the error signal δ

ω

comprising the steps of;

(a) dividing the output of the MAC-2 by the output of the MAC-1;

(b) computing the inverse tangent of the result of step (a);

(c) splitting the output of step (b) into two channels, in the first channel

(d) multiplying the output of step (b) by a constant K₁ and integrating the result over time;

in the second channel

(e) multiplying the output of step (b) by a constant K₂; and

(f) summing the outputs of said first and second channels.

17. The method of claim 13 wherein generating sine and cosine waveforms for each frame comprising the steps of:

(a) setting S<sub>k−

2</sub> to −

sin (ω

T_s+δ

ω

T_s), and S<sub>k−

1</sub> to 0 wherein S<sub>k−

1</sub> and S<sub>k−

2</sub> are the sine-waveforms of the k−

1th and k−

2th samples, respectively;

(b) setting C<sub>k−

2</sub> to cos(ω

T_s+δ

ω

T_s), and C<sub>k−

1</sub> to 1 wherein C<sub>k−

1</sub> and C<sub>k−

2</sub> are the cosine-waveforms of the k−

1th and k−

2th samples, respectively;

(c) computing the term 2cos(ω

T_s+δ

ω

T_s), wherein ω

is the phase increment, T_s is the sampling interval of the ADC, and δ

ω

is the error signal term for correcting the frequency discrepancy;

(d) computing S_k according to the following equation;

18. The method of claim 11 wherein the FDMA signal is electromagnetic signal.

19. A method for coherent detection and demodulation of a FDMA signal being a superposition of amplitude modulated carriers, the method comprising the steps of:

receiving said FDMA electromagnetic signal by a system for detection and demodulation of the signal; and

processing the received signal by using a PLL technique and extracting an envelope of at least one carrier;

wherein processing the signal by using a PLL technique and extracting an envelope of at least one carrier comprising the steps of;

(a) digitizing, framing and shaping the signal;

(b) down-converting the signal obtained in step (a) to a baseband by multiplying the signal on sine and cosine waves synthesized inside PLL;

(c) rejecting envelopes and carriers others than the one of interest by multiplying the signal obtained in step (b) by filter taps; and

(d) computing the envelope of at least one carrier of interest from the result obtained in step (c).

20. The method of claim 19 wherein rejecting envelopes and carriers others than the one of interest is performed by using down-decimating technique, whereby multiplication of the signal by the filter taps is performed only once per frame.