Antenna interface

• US 6,735,418 B1
• Filed: 03/16/2000
• Issued: 05/11/2004
• Est. Priority Date: 05/24/1999
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Intel Corporation
• Inventors: Cho, Thomas B., MacNally, Donald E.
• Primary Examiner(s): APPIAH, CHARLES NANA
• Application Number:
  US09/527,314
• Time in Patent Office: 1,517 Days
• Field of Search: 455/73, 455/80, 455/82, 455/83, 455/319, 455/333, 455/78, 455/79, 455/84, 370/280, 333/103, 333/104, 333/105
• US Class Current: 455/78
• CPC Class Codes: H04B 1/0458 Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages matching circuits in general H03H
• CPC Class Codes: H04B 1/18 Input circuits, e.g. for coupling to an antenna or a transmission line coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H

Abstract

An antenna interface for a Time Division Duplex (TDD) radio transceiver allows a transceiver to be attached to an antenna/filter without the need for an antenna switch. The antenna interface includes a single Balun circuit to convert a single-ended signal to/from differential signals, and a single impedance matching circuit to match an impedance at an output of the single Balun circuit with an input impedance of a Low Noise Amplifier (LNA) of a receiver and to provide an output impedance of a Power Amplifier (PA) of a transmitter. The single impedance matching circuit is coupled to both the LNA and the PA. The LNA and the PA are based on CMOS technology and made within a single integrated circuit.

Claims

1. An antenna interface between an antenna and a transceiver having a receiver and a transmitter, comprising:

a single impedance matching circuit to match an impedance of the antenna with an input impedance of a Low Noise Amplifier (LNA) of the receiver in a receive cycle and to provide an output load impedance of a Power Amplifier (PA) of the transmitter in a transmit cycle, the single impedance matching circuit being coupled to both the LNA and the PA without an intervening switch therebetween;

wherein the PA is off in the receive cycle and provides high impedance in parallel to the input impedance of the LNA, and the LNA is off in the transmit cycle and provides high impedance in parallel to the output load impedance of the PA.

2. The antenna interface of claim 1, wherein the LNA and the PA are based on CMOS technology and made within a single integrated circuit.

3. A Time Division Duplex (TDD) transceiver system, comprising:

an antenna for receiving and transmitting a signal;

a bandpass filter to filter out noise received from the antenna;

an antenna interface coupled between the bandpass filter and a transceiver; and

the transceiver including a receiver having a Low Noise Amplifier (LNA) to amplify a signal received from the antenna interface, and a transmitter having a Power Amplifier (PA) to amplify a signal transmitted to the antenna interface, the receiver and the transmitter being part of a single integrated circuit; and

the antenna interface comprising;

a single impedance matching circuit, coupled between the bandpass filter and the transceiver, to match an impedance at an output of the bandpass filter with an input impedance of the Low Noise Amplifier (LNA) of the receiver and to provide an output load impedance of the Power Amplifier (PA) of the transmitter; and

wherein the single impedance matching circuit is coupled to both the LNA and the PA without an intervening switch therebetween.

4. The Time Division Duplex (TDD) transceiver system of claim 3, wherein the LNA and the PA are based on CMOS technology.

5. An antenna interface for a transceiver having a transmitter and a receiver, comprising:

a single Balun circuit to convert a single-ended signal to/from differential signals;

a single impedance matching circuit to match an impedance at an output of the single Balun circuit with an input impedance of a Low Noise Amplifier (LNA) of the receiver in a receive cycle and to provide an output load impedance of a Power Amplifier (PA) of the transmitter in a transmit cycle, the single impedance matching circuit being coupled to both the LNA and the PA;

wherein the PA is off in the receive cycle and provides high impedance in parallel to the input impedance of the LNA, and the LNA is off in the transmit cycle and provides high impedance in parallel to the output load impedance of the PA.

6. The antenna interface of claim 5, wherein the LNA and the PA are based on CMOS technology and made within a single integrated circuit.

7. A Time Division Duplex (TDD) transceiver system, comprising:

an antenna for receiving and transmitting a signal;

a bandpass filter to filter out noise received from the antenna;

an antenna interface coupled between the bandpass filter and a transceiver;

the transceiver including a receiver having a Low Noise Amplifier (LNA) to amplify a signal received from the antenna interface, and a transmitter having a Power Amplifier (PA) to amplify a signal transmitted to the antenna interface; and

the antenna interface comprising;

a single Balun circuit, coupled to the bandpass filter, to convert a single-ended signal to/from differential signals;

a single impedance matching circuit, coupled to the Balun circuit and the transceiver, to match an impedance at an output of the single Balun circuit with an input impedance of the Low Noise Amplifier (LNA) of the receiver and to provide an output load impedance of the Power Amplifier (PA) of the transmitter; and

wherein the single impedance matching circuit is coupled to both the LNA and the PA without an intervening switch therebetween.

8. The Time Division Duplex (TDD) transceiver system of claim 7, wherein the LNA and the PA are based on CMOS technology and made within a single integrated circuit.