Multithreaded microprocessor with asymmetrical central processing units

• US 6,735,687 B1
• Filed: 06/15/2000
• Issued: 05/11/2004
• Est. Priority Date: 06/15/2000
• Status: Expired due to Fees

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Kok, Jan
• Primary Examiner(s): TSAI, HENRY
• Application Number:
  US09/595,076
• Time in Patent Office: 1,426 Days
• Field of Search: 712/215, 712/205, 712/206, 712/207, 712/203, 712/28, 712/233, 712/234, 712/235, 712/237, 712/34, 712/35, 709/107, 709/108, 709/100, 709/200
• US Class Current: 712/215
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

In addition to the normal circuitry which provides the normal computation, a microprocessor is provided with one or more additional but simplified central processing units which allows additional threads of execution to occur at a slower rate. The purpose of the secondary threads is to prefetch data from external storage to main memory or from main memory to cache in order to minimize waiting by the primary thread.

Claims

1. A single-chip microprocessor comprising:

a first computer processing unit (CPU) comprising a first instruction fetch unit which fetches a first set of instructions and executes a first thread of execution;

a second CPU asymmetrical to said first CPU comprising a second instruction fetch unit which fetches a second set of instructions and executes a second thread of execution; and

an execution unit shared by said first CPU and said second CPU for performing each of said first set of instructions and said second set of instructions.

2. A microprocessor in accordance with claim 1, wherein:

said first CPU comprises a first set of registers; and

said second CPU comprises a second set of registers, said second set of registers being fewer in number than said first set of registers.

3. A microprocessor in accordance with claim 1, wherein:

said first CPU comprises a first set of registers; and

said second CPU comprises a second set of registers, said second set of registers being implemented with simpler circuitry than said first set of registers.

4. A microprocessor in accordance with claim 1, wherein:

said first CPU comprises a first set of registers; and

said second CPU comprises no registers.

5. A microprocessor in accordance with claim 1, wherein:

said first CPU comprises a first instruction decoder that operates on a first set of instruction opcodes; and

said second CPU comprises a second instruction decoder that operates on a second set of instruction opcodes, said second set of instruction opcodes comprising fewer instruction opcodes than said first set of instruction opcodes.

6. A microprocessor in accordance with claim 1, wherein:

said second thread of execution monitors said first thread of execution.

7. A microprocessor in accordance with claim 1, wherein:

said second thread of execution operates to prefetch data from a main memory into a cache used by said first CPU.

8. A microprocessor in accordance with claim 1, wherein:

said second thread of execution operates to prefetch data from an external storage into a main memory accessed by said microprocessor.

9. A microprocessor in accordance with claim 1, wherein:

said second thread of execution operates to prefetch data from one level of memory to a next level of memory.

10. A single-chip microprocessor comprising:

a first computer processing unit (CPU) comprising a first program counter, a first instruction fetch unit which fetches a first set of instructions from a first memory location indicated by said first program counter, and a first instruction decoder which decodes said first set of instructions, said first CPU executing a first thread of execution; and

a second CPU comprising simplified circuitry than said first CPU, said second CPU comprising a second program counter, a second instruction fetch unit which fetches a second set of instructions from a second memory location indicated by said second program counter, and a second instruction decoder which decodes said second set of instructions, said second CPU executing a second thread of execution; and

an execution unit shared by said first CPU and said second CPU for executing each of said first set of instructions and said second set of instructions.

11. A microprocessor in accordance with claim 10, wherein:

said second thread of execution comprises a prefetch algorithm for prefetching data from primary memory into a cache used by said first thread of execution.

12. A microprocessor in accordance with claim 10, wherein:

said second thread of execution comprises a fetch algorithm for prefetching data from external storage into primary memory used by said microprocessor.

13. A microprocessor in accordance with claim 10, wherein:

said first CPU comprises a first set of registers; and

said second CPU comprises a second set of registers, said second set of registers being fewer in number than said first set of registers.

14. A microprocessor in accordance with claim 10, wherein:

said first CPU comprises a first set of registers; and

said second CPU comprises a second set of registers, said second set of registers being implemented with simpler circuitry than said first set of registers.

15. A microprocessor in accordance with claim 10, wherein:

said first CPU comprises a first set of registers; and

said second CPU comprises no registers.

16. A microprocessor in accordance with claim 10, wherein:

said first CPU comprises a first instruction decoder that operates on a first set of instruction opcodes; and

said second CPU comprises a second instruction decoder that operates on a second set of instruction opcodes, said second set of instruction opcodes comprising fewer instruction opcodes than said first set of instruction opcodes.

17. A microprocessor in accordance with claim 10, comprising:

an execution unit shared by said first CPU and said second CPU which executes instructions processed by both said first and second CPUs.

18. A method for increasing the throughput of a single-chip microprocessor, comprising:

providing in said single-chip microprocessor a first computer processing unit (CPU) comprising a first instruction fetch unit which fetches a first set of instructions and executes a first thread of execution;

providing in said single-chip microprocessor a second CPU asymmetrical to said first CPU comprising a second instruction fetch unit which fetches a second set of instructions and executes a second thread of execution; and

providing a single execution shared by said first CPU and said second CPU for performing each of said first set of instructions and said second set of instructions.

19. A method in accordance with claim 18, wherein:

said second thread of execution comprises a prefetch algorithm for prefetching data from primary memory into a cache used by said first thread of execution.

20. A microprocessor in accordance with claim 18, wherein:

said second thread of execution comprises a fetch algorithm for prefetching data from external storage into primary memory used by said microprocessor.