Time frame synchronization of medical monitoring signals

• US 6,735,711 B2
• Filed: 09/21/2001
• Issued: 05/11/2004
• Est. Priority Date: 05/26/1999
• Status: Expired due to Fees

• Current Assignee: Viasys Healthcare Incorporated (Cardinal Health, Inc.)
• Original Assignee: Viasys Healthcare Incorporated (Cardinal Health, Inc.)
• Inventors: Lutz, William J.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Patel, Nitin C.
• Application Number:
  US09/960,011
• Publication Number:
  US 20020055687A1
• Time in Patent Office: 963 Days
• Field of Search: 713/500, 713/501, 713/502, 713/503
• US Class Current: 713/500
• CPC Class Codes: A61B 5/0006 ECG or EEG signals
• CPC Class Codes: A61B 5/377 using evoked responses
• CPC Class Codes: A61B 5/389 Electromyography [EMG]

Abstract

The present invention provides a system and method for establishing a synchronized time frame for signals in a medical monitoring system. In particular, the present invention provides a system and method for synchronizing the time frame of stimulation signals provided by a stimulator to a subject and response signals received by an amplifier device from the subject in response thereto. Thus, the present invention allows accurate display and analysis of the relationship between stimulation and response signals by a monitoring device. Time frame synchronization of stimulus and response signals is achieved using a periodic bus cycle clock signal which is provided by a bus, i.e., an IEEE 1394 bus, connecting together each of the devices in the monitoring system. For example, a time frame synchronized stimulation trigger signal may be generated by a stimulus synchronization circuit including a phase-locked loop for providing a local clock signal synchronized to the periodic bus cycle clock signal, and employing the local clock signal to provide a multi-bit signal indicating a segment during a bus cycle during which the stimulation signal is provided by the stimulator to the subject.

Claims

1. A time frame synchronization circuit for providing time frame synchronization of a first signal with a periodic bus cycle clock signal, comprising:

(a) a means for receiving a first signal;

(b) a means for receiving a periodic bus cycle clock signal;

(c) a phase lock loop circuit for generating a local synchronization circuit clock signal synchronized with the periodic bus cycle clock signal; and

(d) means for generating a multi-bit time frame synchronized signal indicating a segment of a bus cycle of the periodic bus cycle clock signal during which the first signal occurs using the first signal and the local synchronization circuit clock signal.

2. The time frame synchronization circuit of claim 1 comprising additionally a clock divider for deriving a plurality of local clock signals of various frequencies from the local synchronization circuit clock signal.

3. The time frame synchronization circuit of claim 2 wherein the means for generating a multi-bit time frame synchronized signal includes a multi-bit latch having inputs and outputs and wherein selected ones of the plurality of local clock signals are provided to the inputs of the multi-bit latch to provide a varying multi-bit signal dividing the bus cycle into a plurality of segments, and wherein the first signal is provided to the latch to latch the varying multi-bit signal on the inputs of the multi-bit latch onto the outputs of the multi-bit latch to provide the multi-bit time frame synchronized signal.

4. The time frame synchronization circuit of claim 1 wherein the first signal is a stimulation pulse trigger signal provided by a stimulator in a medical monitoring system.

5. The time frame synchronization circuit of claim 1 wherein the periodic bus cycle clock signal is a Cycle Start packet signal in an IEEE 1394 bus.

6. A method of providing time frame synchronization of a first signal with a periodic bus cycle clock signal, comprising the steps of:

(a) receiving a first signal;

(b) receiving a periodic bus cycle clock signal;

(c) generating a local synchronization clock signal synchronized with the periodic bus cycle clock signal; and

(d) generating a multi-bit time frame synchronized signal indicating a segment of a bus cycle of the periodic bus cycle clock signal during which the first signal occurs using the first signal and the local synchronization circuit clock signal.

7. The method of claim 6 wherein the step of generating a multi-bit time frame synchronized signal includes the step of deriving a plurality of local clock signals of various frequencies from the local synchronization clock signal.

8. The method of claim 7 wherein the step of generating a multi-bit time frame synchronized signal includes the further steps of providing selected ones of the plurality of local clock signals to inputs of a multi-bit latch to provide a varying multi-bit signal which divides the bus cycle into a plurality of segments at the inputs of the multi-bit latch, and providing the first signal to the latch to latch the varying multi-bit signal on the inputs of the multi-bit latch onto the outputs of the multi-bit latch to provide the multi-bit time frame synchronized signal.

9. The method of claim 6 wherein the first signal is a stimulation pulse trigger signal provided by a stimulator in a medical monitoring system.

10. The method of claim 6 wherein the periodic bus cycle clock signal is a Cycle Start packet signal in an IEEE 1394 bus.