Method and apparatus for performing extraction using a model trained with bayesian inference
First Claim
1. A method of extracting electrical characteristics from an integrated circuit layout, said method comprising:
- dividing said integrated circuit layout into areas with at least one extraction sub problem each;
determining a set of physical parameters that define said extraction sub problem;
selecting a machine learning model from a plurality of machine-learning models, said machine learning model trained with Bayesian inference;
supplying said set of physical parameters to said machine-learning model; and
calculating at least one electrical characteristic for said extraction sub problem by analyzing said set of physical parameters with said machine-learning model trained with Bayesian inference.
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Abstract
A machine-learning model may be created to perform integrated circuit layout extraction. Using such a machine-learning system has two main phases: model creation and model application. The model creation phase comprises creating one or more extraction models using machine-learning techniques. The machine learning is performed by first creating training data sets composed of the identified parameters from typical examples of the smaller extraction problem and the answers to those example extraction problems as solved using a highly accurate physics-based field solver. Next, the system performs machine learning using Bayesian inference in order to train the neural network models. The Bayesian inference may be implemented with normal Monte Carlo techniques, Hybrid Monte Carlo techniques, or other Bayesian learning techniques. After the creation of a set of models for each of the smaller simpler extraction problems, the machine-learning based models may be used for extraction.
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Citations
18 Claims
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1. A method of extracting electrical characteristics from an integrated circuit layout, said method comprising:
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dividing said integrated circuit layout into areas with at least one extraction sub problem each;
determining a set of physical parameters that define said extraction sub problem;
selecting a machine learning model from a plurality of machine-learning models, said machine learning model trained with Bayesian inference;
supplying said set of physical parameters to said machine-learning model; and
calculating at least one electrical characteristic for said extraction sub problem by analyzing said set of physical parameters with said machine-learning model trained with Bayesian inference. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
determining a capacitance per unit length for a subsection of interconnect wiring; and
multiplying said capacitance per unit length by a length of said subsection of interconnect wiring.
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10. A computer readable medium, said computer readable medium comprising an arranged set of computer instructions for:
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dividing an integrated circuit layout into areas with at least one extraction sub problem each;
determining a set of physical parameters that define said extraction sub problem;
selecting said extraction sub problem model from a plurality of extraction sub problem models, said extraction sub problem model trained by Bayesian inference;
supplying said set of physical parameters to said extraction sub problem model trained with Bayesian inference; and
calculating at least one electrical characteristic for said extraction sub problem by analyzing said set of physical parameters with said machine-learning model trained with Bayesian inference. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
determining a capacitance per unit length for a subsection of interconnect wiring; and
multiplying said capacitance per unit length by a length of said subsection of interconnect wiring.
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Specification
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- Resources
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Current AssigneeCadence Design Systems Incorporated (Cadence Group)
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Original AssigneeCadence Design Systems Incorporated (Cadence Group)
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InventorsTeig, Steven, Chatterjee, Arindam
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Primary Examiner(s)Garbowski, Leigh M.
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Assistant Examiner(s)Rossoshek, Yelena
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Application NumberUS10/062,185Time in Patent Office831 DaysField of Search716/2, 716/5, 716/11, 716/19, 716/4, 716/10, 707/3, 707/104.1, 706/20, 705/8, 705/37, 703/15, 703/19, 382/767, 257/315US Class Current716/115CPC Class CodesG06F 30/367 Design verification, e.g. u...G06N 7/01 Probabilistic graphical mod...
