Chip scale package with flip chip interconnect

• US 6,737,295 B2
• Filed: 02/22/2002
• Issued: 05/18/2004
• Est. Priority Date: 02/27/2001
• Status: Expired due to Term

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Chippac Company Limited
• Inventors: Tam, Samuel, Kweon, Young Do, Chen, Andrea, Pendse, Rajendra, Ahmad, Nazir, Kim, Kyung-Moon
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Roman, Angel
• Application Number:
  US10/081,491
• Publication Number:
  US 20020151189A1
• Time in Patent Office: 816 Days
• Field of Search: 438/108, 257/738, 257/778
• US Class Current: 438/106
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/8114 Guiding structures outside the body
• CPC Class Codes: H01L 2224/81203 Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/8183 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83194 Lateral distribution of the layer connectors
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A flip chip package is formed by a solid-state bond technique for connecting the input/output pads on the integrated circuit chip and the package substrate. The solid-state bond technique involves a direct mating of metal surfaces, and does not employ any particulate conductive material nor any melting or flow of any interconnecting material. Accordingly the connections can be formed at very fine geometries. In another aspect, the space between the surface of the integrated circuit chip and the subjacent surface of the package substrate is filled with a patterned adhesive structure, which consists of one or more adhesive materials that are deployed in a specified pattern in relation to the positions of the second level interconnections between the package and the printed circuit board.

Claims

1. A flip chip package, comprising

an integrated circuit chip having interconnect bumps formed on input/output pads in a specified arrangement in a surface thereof, and a package substrate having a plurality of bond pads in a complementary arrangement in a subjacent surface of the package substrate, wherein

second level interconnect sites are arranged in a second surface of the package substrate, and second level interconnect structures are connected to the respective second level interconnect sites, and wherein

a fill volume is defined between the integrated circuit chip and the package substrate, the fill volume being at least partly filled with at least one fill material, each said fill material having a selected specific elastic modulus, wherein regions of the fill volume that overlie the second level interconnect sites contain a lower specific elastic modulus fill material.

2. The flip chip package of claim 1 wherein the fill volume includes a first fill zone comprising a plurality of generally columnar volumes, generally overlying the plurality of second level interconnect sites;

and the second fill zone consists of the remainder of the fill volume.

3. The flip chip package of claim 2 wherein at least a part of the first fill zone contains a first material having a lower specific elastic modulus, and at least a part of the second fill zone contains a second material having a higher specific elastic modulus.

4. The flip chip package of claim 3 wherein the first fill material has a specific elastic modulus less than about 0.5 GPa.

5. The flip chip package of claim 3 wherein the second fill material has a specific elastic modulus greater than about 5 GPa.

6. The flip chip package of claim 5 wherein the second fill material has a specific elastic modulus in a range about 5 GPa to about 15 GPa.

7. The flip chip package of claim 3 wherein the second fill material comprises an epoxy.

8. The flip chip package of claim 7 wherein the second fill material comprises an anhydride curable epoxy.

9. The flip chip package of claim 3 wherein the first fill zone comprises voids in the fill material within the fill volume.

10. The flip chip package of claim 3 wherein the first fill material comprises an adhesive.

11. The flip chip package of claim 10 wherein the first fill material comprises a silicon adhesive.

12. A method for making a flip chip package configured for interconnection to a printed circuit board, comprising

providing an integrated circuit chip having a surface;

providing a package substrate having a first surface and a second surface, the second surface being provided with a plurality of second level interconnect sites, the locations of the second level interconnect sites defining a plurality of first fill zone areas over the first surface of the package substrate, the remainder of the first surface of the package substrate constituting a second fill zone area;

dispensing at least a second fill material, having a specific elastic modulus greater than about 5 GPa, within the second fill zone area on the first surface of the package substrate; and

assembling the integrated circuit chip and the package substrate so that the second fill material is confined in a second fill zone within a volume defined between the integrated circuit chip surface and the first surface of the package substrate.

13. The method of claim 12 wherein the second fill material has a specific elastic modulus in a range about 5 GPa to about 15 GPa.

14. The method of claim 12, further comprising, prior to assembling the package, dispensing a first fill material having a specific elastic modulus less than about 0.5 GPa within the first fill zone area on the first surface of the package substrate.