Method for manufacturing a thin gate dielectric layer for integrated circuit fabrication

• US 6,737,362 B1
• Filed: 02/28/2003
• Issued: 05/18/2004
• Est. Priority Date: 02/28/2003
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chi-Chun, Wu, Chun-Lin, Chen, Chia Lin, Chen, Shih-Chang, Lee, Tze Liang
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): MAI, ANH D
• Application Number:
  US10/377,568
• Time in Patent Office: 445 Days
• Field of Search: 438/216, 438/287, 438/591, 438/763, 438/778, 438/783, 438/785, 438/786
• US Class Current: 438/776
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

The present disclosure provides a method for forming a gate stack structure for semiconductor devices. The disclosed method comprises steps such as forming a dielectric layer on a substrate; applying a plasma nitridation process on the formed dielectric layer; applying a first anneal process on the deposited dielectric layer; etching the dielectric layer to a predetermined thickness using a diluted etchant; applying a second anneal process using an oxygen environment on the etched dielectric layer after the etching; and forming a gate electrode layer on top of the dielectric layer. The etching makes the top portion of the etched dielectric layer have a significantly higher concentration of nitrogen than the lower portion of the etched dielectric layer so as the leakage current is significantly reduced.

Claims

1. A method for forming a gate oxide layer for devices of small feature sizes, the method comprising:

forming a gate oxide layer on a substrate;

applying a nitridation process on the formed gate oxide layer;

etching the gate oxide layer back to a predetermined thickness after the nitridation process; and

applying an anneal process using an oxygen environment on the etched gate oxide.

2. The method of claim 1 wherein the nitridation process further comprises applying an post-nitridation anneal process on the gate oxide layer.

3. The method of claim 1 wherein the nitridation process is a plasma nitridation process.

4. The method of claim 1 wherein the etching uses diluted etchant.

5. The method of claim 1 wherein the thickness of the gate oxide layer on the substrate is equivalent to about 10 to 25 .ANG of pure oxide.

6. The method of claim 1 wherein the thickness of the d posited gate oxide layer is reduced to a thickness equivalent to about 8 to 15 .ANG of pure oxide after the etching.

7. The method of claim 1 wherein the device feature size is smaller than 0.1 um.

8. The method of claim 1 wherein the etching causes the nitrog n concentration in the top portion of the gate oxide layer to be significantly higher that that in the lower portion.

9. A method for forming a gate stack structure for semiconductor devices of small feature sizes, the method comprising:

forming a gate oxide layer on a substrate for a thickness in a range that is equivalent to 10-25 .ANG of pure oxide;

applying a nitridation process on the formed gate oxide to establish a thin nitride layer;

etching the gate oxide to a thickness in a range that is equivalent to 8-15 .ANG of pure oxide;

applying an anneal process after the etching in an oxygen environment; and

forming a gate electrode layer on top of the gate oxide.

10. The method of claim 9 further comprising applying an anneal process after the nitridation process in an ambient either of oxygen or nitrogen.

11. A method for forming a gate stack structure for semiconductor devices, the method comprising:

forming a dielectric layer on a substrate;

applying a plasma nitridation process on the formed dielectric layer;

applying a first anneal process on the deposited dielectric layer;

etching the dielectric layer to a predetermined thickness using a diluted etchant;

applying a second anneal process using an oxygen environment on the etched dielectric layer after the etching; and

forming a gate electrode layer on top of the dielectric layer,

wherein the etching makes the top portion of the etched dielectric layer have a significantly higher concentration of nitrogen than the lower portion of the etched dielectric layer so that a leakage current is significantly reduced.

12. A method for forming a gate stock structure for semiconductor devices, the method comprising:

forming a dielectric layer on a substrate;

applying a nitridation process on the formed dielectric layer;

etching the dielectric layer to a predetermined thickness of less than the equivalent of 15 .ANG of a pure oxide in terms of its capacitance;

applying an anneal process using an oxygen environment on the dielectric layer after the etching; and

forming a gate electrode layer on top of the dielectric layer,

wherein the etching makes the top portion of the etched dielectric layer have a significantly higher concentration of nitrogen than the lower portion of the etched dielectric layer so that a leakage current is significantly reduced.

13. The method of claim 12 wherein the nitridation process further comprises applying an post-nitridation anneal process on the dielectric layer.

14. The method of claim 12 wherein the nitridation process is a remote plasma nitridation process or a de-couple plasma nitridation process.

15. The method of claim 12 wherein the etching uses a diluted etchant for bett r monitoring a nitrogen profile in the dielectric layer.

16. The method of claim 12 wherein the thickness of the dielectric layer on the substrate is equivalent to about 10 to 25 .ANG of pure oxide in terms of its capacitance for a device having a feature size smaller than 100 nm.

17. The method of claim 16 wherein the thickness of the dielectric layer is reduced to a thickness equivalent to about 8 to 13 .ANG of pure oxide in terms of its capacitance after the etching.