Method for manufacturing a thin gate dielectric layer for integrated circuit fabrication
First Claim
1. A method for forming a gate oxide layer for devices of small feature sizes, the method comprising:
- forming a gate oxide layer on a substrate;
applying a nitridation process on the formed gate oxide layer;
etching the gate oxide layer back to a predetermined thickness after the nitridation process; and
applying an anneal process using an oxygen environment on the etched gate oxide.
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Abstract
The present disclosure provides a method for forming a gate stack structure for semiconductor devices. The disclosed method comprises steps such as forming a dielectric layer on a substrate; applying a plasma nitridation process on the formed dielectric layer; applying a first anneal process on the deposited dielectric layer; etching the dielectric layer to a predetermined thickness using a diluted etchant; applying a second anneal process using an oxygen environment on the etched dielectric layer after the etching; and forming a gate electrode layer on top of the dielectric layer. The etching makes the top portion of the etched dielectric layer have a significantly higher concentration of nitrogen than the lower portion of the etched dielectric layer so as the leakage current is significantly reduced.
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Citations
17 Claims
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1. A method for forming a gate oxide layer for devices of small feature sizes, the method comprising:
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forming a gate oxide layer on a substrate;
applying a nitridation process on the formed gate oxide layer;
etching the gate oxide layer back to a predetermined thickness after the nitridation process; and
applying an anneal process using an oxygen environment on the etched gate oxide. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for forming a gate stack structure for semiconductor devices of small feature sizes, the method comprising:
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forming a gate oxide layer on a substrate for a thickness in a range that is equivalent to 10-25 .ANG of pure oxide;
applying a nitridation process on the formed gate oxide to establish a thin nitride layer;
etching the gate oxide to a thickness in a range that is equivalent to 8-15 .ANG of pure oxide;
applying an anneal process after the etching in an oxygen environment; and
forming a gate electrode layer on top of the gate oxide. - View Dependent Claims (10)
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11. A method for forming a gate stack structure for semiconductor devices, the method comprising:
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forming a dielectric layer on a substrate;
applying a plasma nitridation process on the formed dielectric layer;
applying a first anneal process on the deposited dielectric layer;
etching the dielectric layer to a predetermined thickness using a diluted etchant;
applying a second anneal process using an oxygen environment on the etched dielectric layer after the etching; and
forming a gate electrode layer on top of the dielectric layer, wherein the etching makes the top portion of the etched dielectric layer have a significantly higher concentration of nitrogen than the lower portion of the etched dielectric layer so that a leakage current is significantly reduced.
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12. A method for forming a gate stock structure for semiconductor devices, the method comprising:
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forming a dielectric layer on a substrate;
applying a nitridation process on the formed dielectric layer;
etching the dielectric layer to a predetermined thickness of less than the equivalent of 15 .ANG of a pure oxide in terms of its capacitance;
applying an anneal process using an oxygen environment on the dielectric layer after the etching; and
forming a gate electrode layer on top of the dielectric layer, wherein the etching makes the top portion of the etched dielectric layer have a significantly higher concentration of nitrogen than the lower portion of the etched dielectric layer so that a leakage current is significantly reduced. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification