Substrate connection in an integrated power circuit
First Claim
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1. An integrated circuit, comprising:
- a substrate;
a high-side power transistor in a first region of the substrate;
a low-side power transistor in a second region of the substrate; and
a plurality of barrier regions of the substrate adjacent and separating the first and second regions, each barrier region comprising a barrier transistor and at least one substrate connection connecting the barrier transistor to at least one floating region of the substrate adjacent the barrier region;
wherein, during operation of the integrated circuit, the floating regions and the barrier transistors operate to inhibit operation of parasitic devices associated with the high-side and low-side power transistors.
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Abstract
An integrated circuit is described having a substrate, a power transistor in a first region of the subtracted, and a plurality of barrier regions of the substrate around the first region. Each barrier region includes a barrier transistor and at least one substrate connection connecting the barrier transistor to at least one floating region of the substrate adjacent the barrier region. During operation of the integrated circuit, the floating regions and the barrier transistors operate to inhibit operation of parasitic devices associated with the power transistor
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Citations
41 Claims
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1. An integrated circuit, comprising:
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a substrate;
a high-side power transistor in a first region of the substrate;
a low-side power transistor in a second region of the substrate; and
a plurality of barrier regions of the substrate adjacent and separating the first and second regions, each barrier region comprising a barrier transistor and at least one substrate connection connecting the barrier transistor to at least one floating region of the substrate adjacent the barrier region;
wherein, during operation of the integrated circuit, the floating regions and the barrier transistors operate to inhibit operation of parasitic devices associated with the high-side and low-side power transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. An integrated circuit, comprising:
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a substrate;
a power transistor in a first region of the substrate; and
a plurality of barrier regions of the substrate around the first region, each barrier region comprising a barrier transistor and at least one substrate connection connecting the barrier transistor to at least one floating region of the substrate adjacent the barrier region;
wherein, during operation of the integrated circuit, the floating regions and the barrier transistors operate to inhibit operation of parasitic devices associated with the power transistor. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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Specification