Low dielectric constant shallow trench isolation
First Claim
Patent Images
1. An integrated circuit device, comprising:
- a first active region formed in a substrate;
a second active region formed in the substrate;
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench contains cells of gaseous components; and
a metal interconnect structure located over a portion of the cells of gaseous components and electrically in communication with the first active region and the second active region.
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Accused Products
Abstract
Techniques of shallow trench isolation and devices produced therefrom. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.
106 Citations
29 Claims
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1. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate;
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench contains cells of gaseous components; and
a metal interconnect structure located over a portion of the cells of gaseous components and electrically in communication with the first active region and the second active region. - View Dependent Claims (2, 3, 4)
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5. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate;
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a foamed polymeric material; and
a metal interconnect structure located over a portion of the foamed polymeric material and electrically in communication with the first active region and the second active region. - View Dependent Claims (6, 7, 8)
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9. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate;
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a cured aerogel; and
a metal interconnect structure located over a portion of the cured aerogel and electrically in communication with the first active region and the second active region. - View Dependent Claims (10, 11)
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12. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate;
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with an air gap; and
a conducting layer located over a portion of the air gap, wherein the conducting layer forms a direct interface with the air gap. - View Dependent Claims (13, 14, 15)
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16. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate;
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a foamed polyimide material; and
a metal interconnect structure located over a portion of the foamed polyimide material and electrically in communication with the first active region and the second active region. - View Dependent Claims (17, 18)
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19. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate;
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a foamed Type I polyimide material; and
a metal interconnect structure located over a portion of the foamed Type I polyimide material and electrically in communication with the first active region and the second active region.
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20. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate;
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a foamed Type III polyimide material; and
a metal interconnect structure located over a portion of the foamed Type III polyimide material and electrically in communication with the first active region and the second active region.
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21. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate;
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a foamed polynorbornene material; and
a metal interconnect structure located over a portion of the foamed polynorbornene material and electrically in communication with the first active region and the second active region.
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22. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate;
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a foamed methylsilsesquioxane material; and
a metal interconnect structure located over a portion of the foamed methylsilsesquioxane material and electrically in communication with the first active region and the second active region.
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23. A semiconductor die, comprising:
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an integrated circuit supported by a substrate and having a plurality of semiconductor devices, wherein at least two of the plurality of semiconductor devices are isolated by an interposing trench, and wherein the trench contains cells of gaseous components; and
a metal interconnect structure located over a portion of the cells of gaseous components and electrically in communication with the plurality of semiconductor devices. - View Dependent Claims (24, 25, 26)
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27. A semiconductor die, comprising:
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an integrated circuit supported by a substrate and having a plurality of semiconductor devices, wherein at least two of the plurality of semiconductor devices are isolated by an interposing trench, and wherein the trench is filled with a foamed polymeric material; and
a metal interconnect structure located over a portion of the foamed polymeric material and electrically in communication with the plurality of semiconductor devices.
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28. A semiconductor die, comprising:
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an integrated circuit supported by a substrate and having a plurality of semiconductor devices, wherein at least two of the plurality of semiconductor devices are isolated by an interposing trench, and wherein the trench is filled with a cured aerogel; and
a metal interconnect structure located over a portion of the cured aerogel and electrically in communication with the plurality of semiconductor devices.
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29. A semiconductor die, comprising:
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an integrated circuit supported by a substrate and having a plurality of semiconductor devices, wherein at least two of the plurality of semiconductor devices are isolated by an interposing trench, and wherein the trench is filled with an air gap; and
a conducting layer located over a portion of the air gap, wherein the conducting layer forms a direct interface with the air gap.
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Specification