Clock circuit, GSM phone, and methods of reducing electromagnetic interference

• US 6,737,904 B1
• Filed: 11/12/1999
• Issued: 05/18/2004
• Est. Priority Date: 11/12/1999
• Status: Expired due to Term

• Current Assignee: ST-Ericcson SA (Telefonaktiebolaget LM Ericsson)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Butaud, Remi, Ginetti, Bernard
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US09/439,970
• Time in Patent Office: 1,649 Days
• Field of Search: 327/99, 327/298, 327/291, 327/293, 327/294, 327/299, 331/78, 331/178
• US Class Current: 327/298
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: H04B 15/06 by local oscillators of receivers
• CPC Class Codes: H04B 2215/067 by modulation dispersion

Abstract

A method of producing a clock signal with reduced electromagnetic interference spectral components includes providing a first clock signal; producing a second clock signal by delaying the first clock signal; and generating a jittered clock signal by switching between the first clock signal and the second clock signal at times selected responsive to a random number generator. A GSM phone comprises a clock configured to produce a first clock signal; a delay element coupled to the clock to produce a second clock signal by delaying the first clock signal; a multiplexer coupled to the clock and to the delay element to select between the clock and the delay element; a random number generator coupled to the multiplexer wherein the multiplexer generates a jittered clock signal by switching between the first clock signal and the second clock signal responsive to the random number generator; and a plurality of GSM phone components respectively coupled to the multiplexer to use the jittered clock signal as an input clock for the component.

Claims

1. A method of producing a clock signal with reduced electromagnetic interference spectral components, the method comprising:

providing a first clock signal;

producing a second clock signal by delaying the first clock signal; and

generating a jittered clock signal by switching between the first clock signal and the second clock signal at times selected responsive to a random number generator; and

producing multiple additional clock signals, different from the first and second clock signals, and wherein generating a jittered clock signal comprises generating a jittered clock signal by switching between the first clock signal, the second clock signal, and the additional clock signals, to select any one of the time signals, at times selected responsive to the random number generator; and

providing a multiplexer having binary select inputs, wherein switching between the first clock signal, the second clock signal, and the additional clock signals is performed by the multiplexer, the random number generator being coupled to one of binary select inputs and an additional random number generator being coupled to another of the binary select inputs.

5. A method of producing a clock signal in accordance with claim 1 and further comprising producing a third clock signal, different from the first and second clock signals, by delaying one of the first and second clock signals, and wherein generating a jittered clock signal comprises generating a jittered clock signal by switching between the first clock signal, the second clock signal, and the third clock signal at times selected responsive to the random number generator.

6. A method of producing a clock signal in accordance with claim 1 wherein the first clock has a frequency above 10 MHz and wherein the second clock signal is produced by delaying the first clock signal by less than 2800 picoseconds.

7. A method of producing a clock signal in accordance with claim 1 wherein the first clock has a frequency between 6.5 and 19.5 MHz and wherein the second clock signal is produced by delaying the first clock signal by between 1 and 700 picoseconds.

8. A method of producing a clock signal in accordance with claim 1 wherein the first clock has a frequency between 12.5 and 13.5 MHz and wherein the second clock signal is produced by delaying the first clock signal by between 250 and 450 picoseconds.

2. A method of producing a clock signal with reduced electromagnetic interference spectral components, the method comprising:

providing a first clock signal;

producing a second clock signal by delaying the first clock signal; and

generating a jittered clock signal by switching between the first clock signal and the second clock signal at times selected responsive to a random number generator, wherein the random number generator comprises a plurality of flip-flops chained together, the flip-flops having inputs and outputs, and a logic gate coupled to the flip-flops to perform a logic function based on the outputs of two of the flip-flops and to provide the result of the logic function to the input of one of the flip-flops.

3. A method of producing a clock signal in accordance with claim 2 wherein the random number generator comprises a plurality of flip-flops chained together, the flip-flops having inputs and outputs, and a logic gate coupled to the flip-flops to perform a logic function based on the outputs of two of the flip-flops and to provide the result of the logic function to the first of the flip-flops.

4. A method of producing a clock signal in accordance with claim 2 wherein the random number generator comprises no more than four flip-flops chained together, the flip-flops having inputs and outputs, and no more than one logic gate coupled to the flip-flops to perform a logic function based on the outputs of two of the flip-flops and to provide the result of the logic function to the first of the flip-flops.

9. A method of producing a clock signal that generates reduced electromagnetic interference, the method comprising:

providing a first clock signal;

producing a second clock signal by delaying the first clock signal;

providing a multiplexer having inputs coupled to the first and second clock signals, wherein the multiplexer has multiple additional inputs and has a plurality of binary selection inputs, the method further comprising producing multiple additional clock signals, different from the first and second clock signals and different from each other, and coupling the multiple additional clock signals to respective additional inputs of the multiplexer, and wherein generating a jittered clock signal comprises generating a jittered clock signal by causing the multiplexer to switch between the first clock signal, the second clock signal, and the additional clock signals, to select any one of the time signals, at times selected responsive to a plurality of pseudo-random number generators, different pseudo-random number generators being coupled to different binary selection inputs; and

generating a jittered clock signal using the multiplexer to pseudo-randomly switch between the first clock signal and the second clock signal and the additional clock signals over time.

10. A method of producing a clock signal in accordance with claim 9 wherein pseudo-randomly switching comprises coupling a pseudo-random number generator to the multiplexer, the pseudo-random number generator comprising a plurality of flip-flops chained together, the flip-flops having inputs and outputs, and a logic gate coupled to the flip-flops to perform a logic function based on the outputs of two of the flip-flops and to provide the result of the logic function to the input of one of the flip-flops.

11. A method of producing a clock signal in accordance with claim 9 wherein pseudo-randomly switching comprises coupling a pseudo-random number generator to the multiplexer, the pseudo-random number generator comprising a plurality of flip-flops chained together, the flip-flops having inputs and outputs, and a logic gate coupled to the flip-flops to perform a logic function based on the outputs of two of the flip-flops and to provide the result of the logic function to the first of the flip-flops.

12. A method of producing a clock signal in accordance with claim 9 wherein pseudo-randomly switching comprises coupling a pseudo-random number generator to the multiplexer, the pseudo-random number generator comprising no more than four flip-flops chained together, the flip-flops having inputs and outputs, and no more than one logic gate coupled to the flip-flops to perform a logic function based on the outputs of two of the flip-flops and to provide the result of the logic function to the first of the flip-flops.

13. A method of producing a clock signal in accordance with claim 9 wherein the first clock has a frequency above 10 MHz and wherein the second clock signal is produced by delaying the first clock signal by less than 2800 picoseconds.

14. A method of producing a clock signal in accordance with claim 9 wherein the first clock has a frequency between 6.5 and 19.5 MHz and wherein the second clock signal is produced by delaying the first clock signal by between 1 and 700 picoseconds.

15. A method of producing a clock signal in accordance with claim 9 wherein the first clock has a frequency between 12.5 and 13.5 MHz and wherein the second clock signal is produced by delaying the first clock signal by between 250 and 450 picoseconds.

16. A method of reducing electromagnetic interference in a GSM phone having a plurality of components that use a clock signal, the method comprising:

providing a first clock signal;

producing a second clock signal by delaying the first clock signal;

generating a jittered clock signal by switching between the first clock signal and the second clock signal at times determined responsive to a random number generator;

wherein the random number generator comprises a plurality of flip-flops chained together, the flip-flops having inputs and outputs, and a logic gate coupled to the flip-flops to perform a logic function based on the outputs of two of the flip-flops and to provide the result of the logic function to the input of one of flip-flops;

using the jittered clock signal as a system clock for at least some components of the GSM phone, and

using the jittered clock signal as a system clock for at least some components of the GSM phone.

17. A method of reducing electromagnetic interference in a GSM phone in accordance with claim 16 wherein the random number generator comprises a plurality of flip-flops chained together, the flip-flops having inputs and outputs, and a logic gate coupled to the flip-flops to perform a logic function based on the outputs of two of the flip-flops and to provide the result of the logic function to the first of the flip-flops.

18. A method of reducing electromagnetic interference in a GSM phone in accordance with claim 16 wherein the random number generator comprises no more than four flip-flops chained together, the flip-flops having inputs and outputs, and no more than one logic gate coupled to the flip-flops to perform a logic function based on the outputs of two of the flip-flops and to provide the result of the logic function to the first of the flip-flops.

19. A method of reducing electromagnetic interference in a GSM phone in accordance with claim 16 and further comprising producing a third clock signal, different from the first and second clock signals, by delaying one of the first and second clock signals, and wherein generating a jittered clock signal comprises generating a jittered clock signal by switching between the first clock signal, the second clock signal, and the third clock signal at times selected responsive to the random number generator.

20. A method of reducing electromagnetic interference in a GSM phone in accordance with claim 16 and further comprising producing multiple additional clock signals, different from the first and second clock signals, and wherein generating a jittered clock signal comprises generating a jittered clock signal by switching between the first clock signal, the second clock signal, and the additional clock signals, to select any one of the time signals, at times selected responsive to the random number generator.

21. A method of reducing electromagnetic interference in a GSM phone in accordance with claim 16 wherein the first clock has a frequency above 10 MHz and wherein the second clock signal is produced by delaying the first clock signal by less than 2800 picoseconds.

22. A method of reducing electromagnetic interference in a GSM phone in accordance with claim 16 wherein the first clock has a frequency between 6.5 and 19.5 MHz and wherein the second clock signal is produced by delaying the first clock signal by between 1 and 700 picoseconds.

23. A method of reducing electromagnetic interference in a GSM phone in accordance with claim 16 wherein the first clock has a frequency between 12.5 and 13.5 MHz and wherein the second clock signal is produced by delaying the first clock signal by between 250 and 450 picoseconds.

24. A method of producing a clock signal that generates reduced electromagnetic interference, the method comprising:

providing a first clock signal;

producing a second clock signal by delaying the first clock signal;

producing multiple additional clock signals, different from the first and second clock signals and different from each other; and

generating a jittered clock signal using a multiplexer to pseudo-randomly switch between the first clock signal and the second clock signal and the additional clock signals over time, the multiplexer having inputs coupled to the respective clock signals and having a plurality of binary selection inputs, wherein generating a jittered clock signal comprises generating a jittered clock signal by causing the multiplexer to switch between the first clock signal, the second clock signal, and the additional clock signals, to select any one of the time signals, at times selected responsive to a plurality of pseudo-random number generators, different pseudo-random number generators being coupled to different binary selection inputs, the pseudo-random number generators respectively comprising no more than four flip-flops chained together, the flip-flops having inputs and outputs, and no more than one logic gate coupled to the flip-flops to perform a logic function based on the outputs of two of the flip-flops and to provide the result of the logic function to the first of the flip-flops.