Crosspoint switch with reduced power consumption

• US 6,737,958 B1
• Filed: 11/16/2000
• Issued: 05/18/2004
• Est. Priority Date: 11/16/2000
• Status: Expired due to Fees

• Current Assignee: Free Electron Technology Inc.
• Original Assignee: Free Electron Technology Inc.
• Inventors: Satyanarayana, Srinagesh
• Primary Examiner(s): Horabik, Michael
• Assistant Examiner(s): BANGACHON, WILLIAM L
• Application Number:
  US09/714,706
• Time in Patent Office: 1,279 Days
• Field of Search: 340/14.1, 340/14.69, 340/14.4, 340/2.28, 340/2.26, 340/2.23, 327/407, 327/99, 327/538, 327/362, 330/253, 330/257
• US Class Current: 340/14.1
• CPC Class Codes: H03K 17/6228 using current steering means
• CPC Class Codes: H03K 17/6235 with storage of control signal

Abstract

A crosspoint switch architecture implements high-speed packet switches and incorporates a power-saving bias control circuit with each switch cell. Each switch cell is equipped with two memory cells and a bias control circuit. Power savings are obtained by controlling the bias current of the switch cell as a function of the switch state. Although the additional circuitry accompanying each switch cell adds complexity and a minimal additional power consumption, the power saving realized in the switch cell results in a crosspoint switch with much lower power consumption as compared to existing architectures. The presence of two bits of memory for each switch core allows for fast reconfiguration. The result is an overall power savings and lower cost design.

Claims

1. A matrix type crosspoint switch circuit comprising:

a plurality of input terminals;

a plurality of output terminals;

a plurality of input lines, each connected to a respective input terminal;

a plurality of output lines, each connected to a respective output terminal; and

a switch circuit provided at each intersection of an input line and an output line, each switch circuit comprising a switch cell connected to an input line and an output line, a control terminal for controlling the state of the switch cell, and a bias control circuit coupled to the switch cell, the switch circuits being arranged so that an input signal at any one of the input terminals may be routed to any one of the output terminals in accordance with a signal input to the control terminal;

wherein the bias control circuit is configured to receive configuration information from an external controller and is responsive thereto to provide a control signal to the corresponding switch cell to enable the switch cell supplying a bias current thereto, or to disable the switch cell by supplying no bias current thereto, to reduce the static power dissipation of the switch cell.

2. A matrix type crosspoint switch circuit according to claim 1;

wherein the control signal disables the switch cell when the configuration information indicates that the switch cell is turned OFF.

3. A matrix type crosspoint switch circuit according to claim 1;

wherein the bias provided by the bias circuit is a bias voltage.

4. A matrix type crosspoint switch circuit according to claim 1;

wherein each switch cell comprises a single differential transistor pair and a bias transistor, and each bias control circuit comprises a differential amplifier circuit separate from the differential transistor pair and having a control input configured to receive a signal and wherein in response to the signal the differential amplifier causes the bias voltage provided by the bias control circuit to change to a level that disables the switch cell.

5. A matrix type crosspoint switch circuit according to claim 1;

wherein each switch cell comprises a bias transistor and a single differential amplifier connected to the bias transistor for routing an input signal at an input terminal to a respective output terminal in an ON state of the switch cell, and for turning OFF the bias transistor in an OFF state of the switch cell.

6. A matrix type crosspoint switch circuit according to claim 1;

wherein each switch cell comprises a bias transistor and a single differential amplifier connected to the bias transistor for routing an input signal at an input terminal to a respective output terminal in an ON state of the switch cell, and for turning OFF the bias transistor in an OFF state of the switch cell; and

wherein each bias control circuit comprises a differential amplifier circuit separate from the differential amplifier of the corresponding switch cell and having a control input configured to receive a signal and wherein in response to the signal the differential amplifier causes the bias current provided by the bias transistor of the corresponding switch cell to change to a level that disables the switch cell.

7. A matrix type crosspoint switch circuit according to claim 1;

wherein a driving voltage of the crosspoint switch is no more than 3.3V.

8. A matrix type crosspoint switch circuit according to claim 1;

wherein a driving voltage of the switch circuits is 2.5V.

9. In a high speed logic circuit having a switching circuit for routing data;

wherein the switching circuit comprises a matrix type crosspoint switch circuit according to claim 1.

10. A matrix type crosspoint switch circuit according to claim 1;

wherein each of the switch cells comprises a bias transistor having a base terminal connected to receive the control signal output by the bias control circuit and an emitter terminal connected to a power source voltage, and a single differential transistor pair having emitter terminals connected to a collector of the bias transistor, base terminals connected to a respective input line, and collector terminals connected to a respective output line.

11. A matrix type crosspoint switch circuit according to claim 10;

wherein collector terminals of all of the differential transistor pairs connected to the same output line are joined together.

12. A matrix type crosspoint switch circuit according to claim 10;

further comprising pull-up resistors connected to collector terminals of all of the differential transistor pairs.

13. A matrix type crosspoint switch circuit according to claim 1;

wherein each bias control circuit comprises a differential amplifier separate from the differential transistor pair of the switch cells, and a current follower circuit for providing a first current path which prevents a corresponding switch cell from being turned on and a second current path which turns on the switch cell.

14. A matrix type crosspoint switch circuit according to claim 13;

wherein the bias control circuit further comprises a memory circuit for storing a configuration state of the corresponding switch cell.

15. A matrix type crosspoint switch circuit according to claim 14;

wherein the memory circuit comprises a first latch circuit for storing a current configuration state of the corresponding switch cell and a second latch circuit for storing a subsequent configuration state of the corresponding switch cell.

16. A crosspoint switch circuit comprising:

a plurality of input terminals;

a plurality of output terminals;

a plurality of input lines, each connected to a respective input terminal;

a plurality of output lines, each connected to a respective output terminal; and

a plurality of switch circuits each having a switch cell connected to the input lines and the output lines, a control terminal for controlling the state of the switch cell and a bias control circuit coupled to the switch cell and comprising a differential amplifier and a current follower circuit connected to the differential amplifier for providing a first current path which prevents the switch cell from being turned on and a second current path which turns on the switch cell, the switch circuits being arranged so that an input signal at any one of the input terminals may be routed to any one of the output terminals in accordance with a signal input to the control terminal;

wherein the bias control circuit is configured to receive configuration information from an external controller and is responsive thereto to provide a control signal to the corresponding switch cell to enable the switch cell by supplying a bias current thereto through the second current path, and to disable the switch cell by supplying current through the first current path when the configuration information indicates that the switch cell is turned OFF to thereby minimize loading capacitance, throughput delay and static power dissipation.

17. A crosspoint switch circuit according to claim 16;

wherein the bias provided by the bias circuit is a bias voltage.

18. A crosspoint switch circuit according to claim 16;

wherein each switch cell comprises a single differential transistor pair separate from the differential amplifier of the bias control circuit and a bias transistor connected to the differential transistor pair.

19. A crosspoint switch circuit according to claim 16;

wherein each switch cell comprises a bias transistor and a single differential amplifier connected to the bias transistor for routing an input signal at an input terminal to a respective output terminal in an ON state of the switch cell, and for turning OFF the bias transistor in an OFF state of the switch cell.

20. A crosspoint switch circuit according to claim 16;

wherein the switch circuits comprise multiplexers.

21. A crosspoint switch circuit according to claim 16;

wherein each switch cell comprises a bias transistor and a single differential amplifier connected to the bias transistor for routing an input signal at an input terminal to a respective output terminal in an ON state of the switch cell, and for turning OFF the bias transistor in an OFF state of the switch cell; and

wherein the bias control circuit comprises a differential amplifier circuit separate from the differential amplifier of the switch cell and having a control input configured to receive a signal and wherein in response to the signal the differential amplifier of the bias control circuit causes the bias current provided by the bias transistor of the corresponding switch cell to change to a level that disables the switch cell.

22. A crosspoint switch circuit according to claim 16;

wherein a driving voltage of the switch circuits is no more than 3.3V.

23. A crosspoint switch circuit according to claim 16;

wherein a driving voltage of the switch circuits is 2.5V.

24. In a high speed logic circuit having a switching circuit for routing data;

wherein the switching circuit comprises a crosspoint switch circuit according to claim 16.

25. A crosspoint switch circuit according to claim 16;

wherein each of the switch cells comprises a bias transistor having a base terminal connected to receive the control signal output by the bias control circuit and an emitter terminal connected to a power source voltage, and a single differential transistor pair separate from the differential amplifier of the bias control circuit and having emitter terminals connected to a collector terminal of the bias transistor, base terminals connected to a respective input line, and collector terminals connected to a respective output line.

26. A crosspoint switch circuit according to claim 25;

wherein collector terminals of all of the differential transistor pairs connected to the same output line are joined together.

27. A crosspoint switch circuit according to claim 26;

further comprising pull-up resistors connected to collector terminals of all of the differential transistor pairs.

28. A crosspoint switch circuit according to claim 16;

wherein the bias control circuit further comprises a memory circuit for storing a configuration state of a corresponding switch cell.

29. A crosspoint switch circuit according to claim 28;

wherein the memory circuit comprises a first latch circuit for storing a current configuration state of the corresponding switch cell and a second latch circuit for storing a subsequent configuration state of the corresponding switch cell.