Direct read of DRAM cell using high transfer ratio

• US 6,738,300 B2
• Filed: 08/26/2002
• Issued: 05/18/2004
• Est. Priority Date: 08/26/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Barth, John E. Jr.
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US10/228,142
• Publication Number:
  US 20040037138A1
• Time in Patent Office: 631 Days
• Field of Search: 365/203, 365/196, 365/205, 365/189.04, 365/207, 365/104
• US Class Current: 365/203
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A sensing circuit for performing a direct read of a DRAM memory cell by using a high transfer ratio and a single ended read of a single bitline, wherein a limited number of memory cells are connected to the single bitline to limit the capacitance thereof to provide the high transfer ration. The direct read circuit includes four transistor devices, with three devices preferentially being nFETs. The direct read circuit provides a self-timed write back of data to a memory cell after the data is destructively read from the memory cell in a read operation, provides significant electrical power savings relative to prior art read circuits, as a read operation of a data 0 does not utilize any significant electrical power, and in a folded bitline architecture provides improved noise immunity as each non-active bitline shields an adjacent active bitline.

Claims

1. A circuit for performing precharge in a memory system, the circuit comprising:

a memory cell;

a local bitline;

a wordline coupling said memory cell to said local bitline;

a global bitline;

a first transistor having its gate connected to said global bitline, its source terminal connected to a first power supply and its drain terminal connected to said local bitline;

a second transistor having its gate connected to said local bitline, its source terminal connected to a second power supply and its drain terminal connected to said global bitline;

a third transistor having its gate connected to a read signal, its drain terminal connected to said local bitline and its source terminal connected to a fourth transistor at its drain terminal; and

said fourth transistor having its gate connected to said global bitline.

2. The circuit of claim 1 wherein:

said first transistor is a p-type transistor;

said second, third and fourth transistors are n-type transistors;

said first power supply is positive VDD and said second power supply is ground.

3. The circuit of claim 1, wherein:

said first transistor is an n-type transistor;

said second, third and fourth transistors are p-type transistors; and

said first power supply is ground and said second power supply is VDD.

4. The circuit of claim 1, wherein said memory cell is a DRAM memory cell.

5. The circuit of claim 1, wherein said memory cell is a SRAM memory cell.

6. The circuit of claim 1, wherein said memory cell is a ROM memory cell.

7. The circuit of claim 1, wherein a transfer ratio (C_cell/(C_b1+C_cell)) of the circuit is substantially close or equal to 0.5.

8. The circuit of claim 7, wherein a limited number of memory cells are connected to the local bitline to limit the capacitance of the local bitline to provide a high transfer ratio.

9. The circuit of claim 1, wherein the first transistor comprises a pFET device, and each of the second, third and fourth transistors comprises an nFET device.

10. The circuit of claim 1, wherein the local bitline is precharged to ground and the global bitline is precharged to VDD.

11. The circuit of claim 10, wherein the global bitline is precharged to VDD by turning on a fifth transistor connected between the global bitline and VDD, and VDD on the global bitline precharges the local bitline to ground by turning on the fourth transistor, with the third transistor being activated by an active read signal.

12. The circuit of claim 6, wherein prior to a read operation, the local bitline is taken out of precharge by turning off the third transistor, thus floating the local bitline.

13. The circuit of claim 1, wherein the memory cell comprises a DRAM memory cell connected in an array of DRAM memory cells.

14. The circuit of claim 1, wherein for a read operation of a data 1, the charge in the memory cell representative of a data 1 is shared with the local bitline, coupling the local bitline to a sufficiently high voltage to turn on the second transistor, which drives the local bitline to VDD and discharges the global bitline, and when the global bitline is discharged to VDD minus the threshold voltage of the first transistor, the first transistor turns on and replenishes the local bitline and the cell node at the positive side of the cell to VDD, and the second transistor drives the global bitline to ground.

15. The circuit of claim 11, wherein for a write function the global bitline is driven with either a write data 0 signal to the gate of the fifth transistor, or by a write data 1 signal to the gate of a sixth transistor connected between the global bitline and ground.

16. The circuit of claim 11, wherein the local bitline is precharged to ground by driving the global bitline high with activating signals to the gates of the third and the fifth transistors.

17. The circuit of claim 1, wherein for a destructive read operation of a data 1, the charge in the memory cell representative of the data 1 is shared with the local bitline, and is written back into the cell at the completion of the read operation by a self-timed write back of data to a memory cell after the data is destructively read from the memory cell in the read operation, wherein the second transistor is turned on to automatically write a data 1 back into the memory cell without an external timing signal.

18. The circuit of claim 1, wherein a read operation of a data 0 does not utilize any significant electrical power as no transistors are turned on.

19. The circuit of claim 1, wherein first and second local bitlines are coupled to the global bitline, and only one bitline is sensed at a time in a time multiplex mode, and the unsensed bitline is held at ground precharge, such that operations of the two bitlines do not interfere with each other.

20. The circuit of claim 1, in a folded bitline architecture having first and second local bitlines, each of which is connected to every other memory cell of a memory array, and a wordline is connected to every other local bitline, and the circuit provides improved noise immunity as each non-active bitline shields adjacent bitlines from the active bitline.