Diversity reception method and diversity receiver

• US 6,738,439 B1
• Filed: 01/31/2000
• Issued: 05/18/2004
• Est. Priority Date: 02/02/1999
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Yamamoto, Takeshi, Okanoue, Kazuhiro, Osawa, Tomoki
• Primary Examiner(s): Bocure, Tesfaldet
• Assistant Examiner(s): Ghulamali, Qutbuddin
• Application Number:
  US09/494,588
• Time in Patent Office: 1,569 Days
• Field of Search: 375/347, 375/267, 375/340, 370/328, 370/329, 370/334, 370/339, 370/349, 370/389, 455/132, 455/137
• US Class Current: 375/347
• CPC Class Codes: H04B 7/0814 based on current reception conditions, e.g. switching to different antenna when signal level is below threshold
• CPC Class Codes: H04L 1/06 using space diversity
• CPC Class Codes: H04W 28/06 Optimizing the usage of the radio link, e.g. header compression, information sizing , discarding information system modifying transmission characteristic according to link quality by modifying frame length H04L1/0007; dynamic adaptation of the packet size for flow control or congestion control H04L47/365

Abstract

A diversity receiver having n (integer of 2 or more) antenna branches for receiving a packet made up of a preamble field and data field includes n first switches, second switch, packet detection circuit, and demodulation section. The n first switches receive signals respectively received by the n antenna branches and a “packet receive pulse” representing that a packet is being received, and change the output destination based on the “packet receive pulse”. The second switch receives an antenna switching signal and outputs from the n first switches, and when no “packet receive pulse” is output, selects and outputs the outputs from the n first switches based on the antenna switching signal. The packet detection circuit receives an output from the second switch, and when a packet is being received, outputs a “packet receive pulse”. The demodulation section receives and demodulates all or some of the outputs from the n first switches when a “packet receive pulse” is input.

Claims

1. A diversity reception method for a diversity receiver having n (integer not smaller than 2) antenna branches for receiving a packet made up of a preamble field and data field, comprising the steps of:

switching the n antenna branches to detect packet arrival when no packet arrival is detected;

stopping switching the n antenna branches when packet arrival is detected;

energizing demodulating means in response to the detected packet arrival;

performing reception operation by demodulating the packet based on all signals received by the n antenna branches after packet detection; and

receiving and adding outputs from the demodulation means by an addition circuit when a “

packet receive pulse”

is input.

2. A diversity receiver having n (integer not smaller than 2) antenna branches for receiving a packet made up of a preamble field and data field, comprising:

n first switches for receiving signals respectively received by the n antenna branches and a “

packet receive pulse”

representing that the packet is being received, and changing an output destination based on the “

packet receive pulse”

;

a second switch for receiving an antenna switching signal and outputs from said n first switches, and when no “

packet receive pulse”

is output, selecting and outputting the outputs from said n first switches based on the antenna switching signal;

a packet detection circuit for receiving an output from said second switch, and when the packet is being received, outputting the “

packet receive pulse”

;

an antenna switching control circuit for outputting said antenna switching signal when the “

packet receive pulse”

is not input;

a demodulation section for receiving and demodulating all or some of the outputs from said n first switches when the “

packet receive pulse”

is input.

3. A receiver according to claim 2, wherein said demodulation section comprises demodulation circuits for receiving and demodulating all or some of the outputs from said n first switches when the “

packet receive pulse”

is input, and an addition circuit for receiving and adding outputs from said demodulation circuits when the “

packet receive pulse”

is input.

4. A receiver according to claim 3, wherein said demodulation circuits and said addition circuit are of analog type, and an A/D converter and digital demodulation circuit are arranged on an output side of said demodulation circuits and said addition circuit.

5. A receiver according to claim 2, wherein said demodulation section comprises an addition circuit for receiving and adding all or some of the outputs from said n first switches when the “

packet receive pulse”

is input, and a demodulation circuit for receiving an output from said addition circuit, and operating only when the “

packet receive pulse”

is input.

6. A receiver according to claim 5, wherein said addition circuit and said demodulation circuit are of analog type, and an A/D converter and digital demodulation circuit are arranged on an output side of said addition circuit and said demodulation circuit.

7. A receiver according to claim 3, wherein each of said demodulation circuits comprises a first input terminal for receiving a signal from a corresponding first switch, a second input terminal for receiving the “

packet receive pulse”

, a quadrature demodulation circuit for receiving the signal input to said first input terminal, a baseband demodulation circuit for receiving a demodulated signal from said quadrature demodulation circuit and outputting a demodulation result to an output terminal, and a switch for applying a power supply voltage to said quadrature demodulation circuit and baseband demodulation circuit only when the “

packet receive pulse”

is input.

8. A receiver according to claim 3, wherein each of said demodulation circuits comprises a first input terminal for receiving a signal from a corresponding first switch, a second input terminal for receiving the “

packet receive pulse”

, a quadrature demodulation circuit for receiving the signal input to said first input terminal, a baseband demodulation circuit for receiving a demodulated signal from said quadrature demodulation circuit and outputting a demodulation result, a multiplier for multiplying the demodulation result of said baseband demodulation circuit and outputting a product to an output terminal, a power detection circuit arranged between said quadrature demodulation circuit and multiplier to detect power of said quadrature demodulation circuit, and a switch for applying a power supply voltage to said quadrature demodulation circuit, said baseband demodulation circuit, and said multiplier only when the “

packet receive pulse”

is input.

9. A receiver according to claim 4, wherein each of said demodulation circuits comprises a first input terminal for receiving a signal from a corresponding first switch, a second input terminal for receiving the “

packet receive pulse”

, a quadrature demodulation circuit for receiving the signal input to said first input terminal, and a switch for applying power voltage to said quadrature demodulation circuit only when the “

packet receive pulse”

is input.

10. A receiver according to claim 2, wherein said packet detection circuit comprises:

an average power detection circuit for calculating an average power of a signal input from said second switch;

a memory for storing a packet detection threshold as a threshold for detecting packet arrival;

a comparison circuit for comparing an output from said average power detection circuit with the packet detection threshold when no “

packet receive pulse”

is input, determining that packet arrival is detected and outputting a packet arrival detection pulse when the output from said average power detection circuit exceeds the packet detection threshold, and not comparing the output from said average power detection circuit with the packet detection threshold when the “

packet receive pulse”

is input; and

a hold circuit for holding the packet detection pulse over a duration time of the packet and outputting the packet detection pulse as the “

packet receive pulse”

when the “

packet receive pulse”

is input.

11. A receiver circuit according to claim 2, wherein said antenna switching control circuit comprises:

a clock circuit having as a period a time during which signals respectively received by said n antenna branches are observed; and

a counter which is reset when the “

packet receive pulse”

is input, and cyclically counts up from 1 to n based on an output from said clock circuit to output n count values as antenna switching signals when no “

packet receive pulse”

is input.

12. A diversity receiver having n (integer not smaller than 2) antenna branches for receiving a packet made up of a preamble field and data field, comprising:

(n−

1) first switches for receiving signals respectively received by (n−

1) antenna branches and a “

packet receive pulse”

representing that the packet is being received, and changing an output destination based on the “

packet receive pulse”

;

a second switch for receiving an antenna switching signal and outputs from said (n−

1) first switches, and when no “

packet receive pulse”

is output, selecting and outputting the outputs from said (n−

1) first switches based on the antenna switching signal;

one (n−

(n−

1)) antenna branch which is not connected to said first switches, and always directly outputs a reception signal to said second switch regardless of input/non-input of the “

packet receive pulse”

;

one specific demodulation circuit for receiving a signal received by said (n−

(n−

1)) antenna branch via said second switch to always perform demodulation operation;

a packet detection circuit for receiving a demodulated signal from said specific demodulation circuit, and when the packet is being received, outputting the “

packet receive pulse”

; and

a demodulation section for receiving and demodulating all or some of the outputs from said (n−

1) first switches when the “

packet receive pulse”

is input.

13. A receiver according to claim 12, wherein said specific demodulation circuit comprises an input terminal for receiving a signal from said (n−

(n−

1)) antenna branch, a quadrature demodulation circuit for demodulating the input signal, an output terminal for outputting a demodulated signal from said quadrature demodulation circuit to said packet detection circuit, and a baseband demodulation circuit for receiving the demodulated signal from said quadrature demodulation circuit and outputting a demodulation result.