Parallel bit correlator

• US 6,738,794 B2
• Filed: 04/10/2001
• Issued: 05/18/2004
• Est. Priority Date: 04/10/2001
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Stein, Yosef, Primo, Haim
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US09/829,681
• Publication Number:
  US 20020147825A1
• Time in Patent Office: 1,134 Days
• Field of Search: 708/212, 708/422
• US Class Current: 708/212
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06F 2207/025 String search, i.e. pattern matching, e.g. find identical word or best match in a string
• CPC Class Codes: G06F 7/02 Comparing digital values G06F7/06, G06F7/22, G06F7/38 take precedence

Abstract

A parallel bit correlator for recognizing a predetermined bit pattern including a predefined number m of bits in a stream of data bits including identifying successive sets of m bits in a stream of data bits and simultaneously comparing each of the sets of m bits to the predetermined bit pattern for detecting the presence of the predetermined bit pattern in the stream of data.

Claims

1. A parallel bit correlator for recognizing a predetermined bit pattern including a predefined number m of bits in a stream of data bits comprising:

an array of logic cells;

a bit mask enabling circuit for enabling a number of sets of m logic cells corresponding to successive sets of m bits in a stream of data bits;

a pattern bit loading circuit for each logic cell holding a bit of the predetermined bit pattern; and

a detection circuit for simultaneously comparing each of said sets of m bits with the predetermined bit pattern.

2. The parallel bit correlator of claim 1 in which said array of logic cells is arranged in rows and columns and said sets of m logic cells are disposed in successive rows and columns.

3. The parallel bit correlator of claim 2 in which each logic cell concludes an AND gate.

4. The parallel bit correlator of claim 3 in which each set of m logic cells includes a NOR gate responsive to the AND gate of each of the associated logic cells.

5. The parallel bit correlator of claim 4 in which said enabling circuit includes a first bistable device for enabling said AND gate.

6. The parallel bit correlator of claim 5 in which said means for storing includes a second bistable device for holding the value of a bit of sent bit pattern.

7. A programmable logic device including a parallel bit correlator comprising:

an array of logic cells;

a bit mask enabling circuit for enabling a number of sets of m logic cells corresponding to successive sets of m bits in a stream of data bits;

a pattern bit loading circuit for each logic cell holding a bit of the predetermined bit pattern; and

a detection circuit for simultaneously comparing each of said sets of m bits with the predetermined bit pattern.

8. The programmable logic device of claim 7 in which said array of logic cells is arranged in rows and columns and said sets of m logic cells are disposed in successive rows and columns.

9. The programmable logic device of claim 8 in which each logic cell concludes an AND gate.

10. The programmable logic device of claim 9 in which each set of m logic cells includes a NOR gate responsive to the AND gate of each of the associated logic cells.

11. The programmable logic device of claim 10 in which said enabling circuit includes a first bistable device for enabling said AND gate.

12. The programmable logic device of claim 11 in which said means for storing includes a second bistable device for holding the value of a bit of sent bit pattern.