Cross-bar matrix for connecting digital resources to I/O pins of an integrated circuit
DCFirst Claim
1. A circuit for assigning digital resources to pins of an integrated circuit, comprising:
- a plurality of the pins of said integrated circuit;
a microprocessor formed in said integrated circuit;
a plurality of selectable digital resources formed in said integrated circuit, each of said digital resources having at least two interface signal paths that require interface to at least two of said plurality of pins that are selected; and
a cross-bar matrix having a plurality of signal inputs coupled respectively to the at least two interface signal paths of select ones of said digital resources, and a plurality of signal outputs coupled to the pins of said integrated circuit, said cross-bar matrix controlled by said microprocessor for selectively coupling said ones of said signal inputs to different said signal outputs, whereby the at least two interface signal paths of select ones of said digital resources can be coupled to different ones of said plurality of pins under control of said microprocessor.
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Abstract
A matrix of routing cells forming a cross-bar decoder (310). Signal triplets are coupled through the cross-bar decoder (310) based on control by a microprocessor. A register (50) provide control signals to the cross-bar decoder (310) to either activate or deactivate routing of the triplet signals through cells of the cross-bar decoder (310). The routing cells are arranged in a matrix of columns and rows. Each row of cells is associated with a common data signal input, and each column of the matrix is associated with a common I/O pin. The cells are individually enabled by the microprocessor so that any data signal can be coupled to any of the I/O pins. In addition to routing data signals through the cells, other signals are also routed through the cells.
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Citations
20 Claims
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1. A circuit for assigning digital resources to pins of an integrated circuit, comprising:
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a plurality of the pins of said integrated circuit;
a microprocessor formed in said integrated circuit;
a plurality of selectable digital resources formed in said integrated circuit, each of said digital resources having at least two interface signal paths that require interface to at least two of said plurality of pins that are selected; and
a cross-bar matrix having a plurality of signal inputs coupled respectively to the at least two interface signal paths of select ones of said digital resources, and a plurality of signal outputs coupled to the pins of said integrated circuit, said cross-bar matrix controlled by said microprocessor for selectively coupling said ones of said signal inputs to different said signal outputs, whereby the at least two interface signal paths of select ones of said digital resources can be coupled to different ones of said plurality of pins under control of said microprocessor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A cross-bar matrix, comprising:
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a plurality of matrix cells arranged in rows and columns, each said row of cells associated with a common signal input from a digital resource, which said digital resource is has at least two interface signal paths that are required to be coupled to at least two of said rows of cells, and each column of cells associated with a common signal output; and
each said cell having a control input for controlling whether the cell is to couple a signal on the associated common signal input to the common signal output associated with the cell, whereby any input signal of the row can be coupled to any signal output with the coupling being such that the grouping of signal outputs is functionally associated with said digital resource. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A cross-bar matrix, comprising:
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a plurality of cells arranged in rows and columns, each cell in the row associated with a common data signal, and each cell in the row associated with a common output enable signal, and each cell in the column associated with a common I/O pin;
each cell in the row receiving a different enable signal for enabling the respective cell to couple the data signal and the output enable signal to the respective I/O pin, each cell in the row including a data signal circuit responsive to the enable signal for coupling therethrough the data signal, and each cell in the row including an output enable signal circuit responsive to the enable signal for coupling therethrough the output enable signal; and
each cell in the row including a data receive circuit for receiving the data signal from the respective I/O pin, and responsive to said enable signal for coupling the data receive signal from the I/O pin to a data resource wherein said data resource has at least two interface signal paths that require coupling to at least two respective ones of said I/O pins, such that I/O pins can be grouped with an associated said data resource. - View Dependent Claims (19, 20)
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Specification