System and method for managing data in memory for reducing power consumption

• US 6,738,861 B2
• Filed: 09/20/2001
• Issued: 05/18/2004
• Est. Priority Date: 09/20/2001
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lawrence, Richard H.
• Primary Examiner(s): Sparks, Donald
• Assistant Examiner(s): CHACE, CHRISTIAN
• Application Number:
  US09/957,370
• Publication Number:
  US 20030056067A1
• Time in Patent Office: 971 Days
• Field of Search: 365/203, 365/222, 365/227, 711/106, 711/156, 711/166, 711/170, 711/171, 711/172, 711/173, 713/320
• US Class Current: 711/106
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type. The claimed subject matter relates to organizing data in a memory for a refresh operation.

Claims

1. A system comprising:

a processor;

a memory, coupled to the processor, with a plurality of banks; and

the system to instruct the memory to store a plurality of information in at least one of the plurality of banks based at least in part on a data type of the information and for the memory to execute a refresh operation based at least in part on the data type of the information.

2. The system of claim 1 wherein the memory is a low-power synchronous dynamic random access memory.

3. The system of claim 1 wherein the refresh operation is a partial array self refresh.

4. The system of claim 1 wherein the system is at least one of a personal digital assistant, a cellular phone, an Internet tablet, a personal computer system.

5. The system of claim 1 wherein the data type is at least one of a working storage type that is used during execution of a program, or a long-term type that is used indefinitely.

6. The system of claim 2 wherein the low-power synchronous dynamic random access memory comprises an Extended Mode Register.

7. The system of claim 5 wherein the refresh operation is executed on the plurality of banks which store the long-term data type.

8. An article comprising:

a storage medium having stored thereon instructions, that, when executed by a computing platform, result in execution of a refresh operation by;

partitioning at least one of a plurality of memory banks based at least in part on a data type; and

refreshing at least a fractional portion of one of the plurality of memory banks based at least in part on the data type.

9. The article of claim 8, wherein said storage medium further has stored instructions thereon that, when executed, result in setting a three bit field of an extended mode register of a low-power synchronous dynamic random access memory.

10. The article of claim 8, wherein the data type is either a working storage type that is used during execution of a program or a long-term type that is used indefinitely.

11. A method comprising:

partitioning at least one of a plurality of memory banks based at least in part on a data type;

setting a value in a register; and

refreshing at least one of the plurality of memory banks based at least in part on the value.

12. The method of claim 11 wherein the register is an extended mode register.

13. The method of claim 11 wherein the plurality of memory banks reside in a low-power synchronous dynamic random access memory.

14. The method of claim 11 wherein the value is a three bit field and indicates one, two or four memory banks to be refreshed.