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Modifying a hierarchical representation of a circuit to process composite gates

  • US 6,738,958 B2
  • Filed: 09/10/2001
  • Issued: 05/18/2004
  • Est. Priority Date: 09/10/2001
  • Status: Active Grant
First Claim
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1. A method for analyzing a layout related to a circuit on a semiconductor chip, comprising:

  • receiving a design hierarchy specifying the layout of the circuit, including a set of hierarchically-organized nodes;

    wherein a given node in the design hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes located under the given node in the design hierarchy;

    modifying the design hierarchy to produce a modified design hierarchy by, examining a set of sibling nodes that are located under a parent node in the design hierarchy, identifying a set of interacting geometrical features between the set of sibling nodes, and moving the set of interacting geometrical features from the sibling nodes to the parent node, so that the interaction is visible at the parent node, wherein other geometrical features that do not interact remain at the sibling nodes and are not moved to the parent node;

    performing an analysis on the modified design hierarchy;

    identifying other sets of sibling nodes with equivalent sets of interacting geometrical features; and

    using results from analyzing the set of interacting geometrical features in analyzing the equivalent sets of interacting geometrical features, so that the analysis does not have to be repeated for the equivalent sets of interacting geometrical features;

    wherein performing the analysis involves analyzing the set of interacting geometrical features at the parent node.

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