Methods of forming DRAM assemblies, transistor devices, and openings in substrates

• US 6,740,574 B2
• Filed: 11/06/2002
• Issued: 05/25/2004
• Est. Priority Date: 09/02/1999
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ping, Er-Xuan, Gonzalez, Fernando
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US10/289,916
• Publication Number:
  US 20030073298A1
• Time in Patent Office: 566 Days
• Field of Search: 438/595, 438/589, 438/270, 438/386, 438/424, 438/430, 438/243
• US Class Current: 438/595
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

The invention encompasses a method of forming an opening in a substrate. A first expanse of a first material is formed over the substrate, and such expanse comprises a sidewall edge. A second material is formed along the sidewall edge, and subsequently a second expanse of the first material is formed over the substrate and separated from the first expanse by the second material. The first and second expanses together define a mask. The second material is removed with an etch selective for the second material relative to the first material to form an opening extending through the mask. The substrate is etched through the opening in the mask to extend the opening into the substrate. In a particular embodiment of the invention, the opening is filled with insulative material to form a trenched isolation region. In another embodiment of the invention, the opening is filled with a conductive material to form a transistor gate.

Claims

1. A method of forming an opening in a substrate, comprising:

forming a first layer of a first material over a semiconductor substrate;

forming a pair of blocks over the first layer, the blocks being separated by a gap;

forming spacers of the first material within the gap to narrow the gap;

forming a second layer within the gap, the blocks and second layer together defining a mask;

removing the spacers with an etch selective for the first material relative to the second layer and blocks to form openings in the mask; and

etching through the first layer and into the substrate through the openings in the mask.

2. The method of claim 1 wherein the substrate comprises monocrystalline silicon.

3. The method of claim 1 wherein the substrate comprises monocrystalline silicon, the first material comprises silicon nitride, the blocks comprise silicon dioxide, and the second layer comprises silicon dioxide.

4. A method of forming a trench in a semiconductive material substrate, comprising:

forming a silicon nitride layer over a semiconductor substrate;

forming a pair of silicon dioxide blocks over and physically against the silicon nitride layer and spaced from one another by a gap;

forming a silicon layer over the silicon nitride layer and in the gap between the blocks;

forming silicon nitride spacers along sidewall edges of the blocks;

the silicon nitride spacers covering a first portion of the silicon layer and not covering a second portion of the silicon layer;

oxidizing the second portion of the silicon layer to convert the second portion to silicon dioxide;

removing the silicon nitride spacers with an etch selective for silicon nitride relative to the silicon dioxide;

the removing of the silicon nitride spacers leaving a silicon dioxide mask over the semiconductor substrate, the silicon dioxide mask comprising the pair of silicon dioxide blocks and the silicon dioxide of the converted second portion, the silicon dioxide mask having openings extending therethrough to the first portion of the silicon layer;

removing the first portion of the silicon layer from within the openings to expose the silicon nitride layer within the openings; and

extending the openings through the silicon nitride layer and into the semiconductor substrate to form at least one trench extending into the substrate.

5. The method of claim 4 further comprising filling the trench in the substrate with an insulative material to form a trenched isolation region.

6. The method of claim 4 further comprising:

filling the trench in the semiconductor substrate with silicon dioxide; and

utilizing the silicon nitride layer as an etch stop during a polishing process to form a planarized upper surface over the semiconductor substrate.

7. The method of claim 6 wherein the silicon dioxide is formed in the trench by high density plasma silicon dioxide deposition.

8. The method of claim 6 wherein the semiconductor substrate comprises silicon and the filling the trench with silicon dioxide comprises:

thermally growing a thin layer of oxide over walls of the silicon-comprising substrate within the trench to partially fill the trench; and

deposition of high density plasma silicon dioxide to fill a remainder of the partially filled trench.

9. A method of forming a transistor device supported by a semiconductive material substrate, comprising:

forming a silicon nitride layer over a semiconductor substrate;

forming a pair of silicon dioxide blocks over the silicon nitride layer and spaced from one another by a gap;

forming a silicon layer over and physically against the silicon nitride layer and in the gap between the blocks;

forming silicon nitride spacers along sidewall edges of the blocks;

the silicon nitride spacers covering a first portion of the silicon layer and not covering a second portion of the silicon layer;

oxidizing the second portion of the silicon layer to convert the second portion to silicon dioxide;

removing the silicon nitride spacers with an etch selective for silicon nitride relative to the silicon dioxide;

the removing of the silicon nitride spacers leaving a silicon dioxide mask over the semiconductor substrate, the silicon dioxide mask comprising the pair of silicon dioxide blocks and the silicon dioxide of the converted second portion, the silicon dioxide mask having openings extending therethrough to the first portion of the silicon layer;

removing the first portion of the silicon layer from within the openings to expose the silicon nitride layer within the openings;

extending the openings through the silicon nitride layer and into the semiconductor substrate to form at least one trench extending into the substrate, the trench having walls;

forming an insulative material along the trench walls to partially fill the trench and leaving a narrowed opening within the trench;

filling the narrowed opening with a conductive material; and

forming source/drain regions extending into the substrate and separated from the conductive material by the insulative material over the trench walls.

10. The method of claim 9 wherein the substrate comprises silicon, and wherein the forming the insulative material over the trench walls comprises oxidizing the silicon of the trench walls to form silicon dioxide.

11. The method of claim 9 wherein the filling the narrowed trench with conductive material comprises filling the narrowed trench with conductively doped polysilicon.

12. The method of claim 9 wherein the conductive material formed within the trench comprises conductively doped polysilicon, and the method further comprises forming a diffusion region beneath the conductively doped polysilicon.

13. The method of claim 9 wherein the conductive material formed within the trench comprises conductively doped polysilicon, and wherein one of the source/drain regions extends to beneath the conductively doped polysilicon.

14. The method of claim 9 wherein the silicon dioxide blocks are physically against the silicon nitride layer.