Integrated circuits and methods for their fabrication
First Claim
1. A method for fabricating an integrated circuit, the method comprising:
- (a) providing a body having one or more openings in a first side;
(b) fabricating a first dielectric and a conductor in each of the one or more openings with the conductor in each of the openings being separated from the body by the first dielectric;
(c) removing material of the body from a second side of the body to expose the first dielectric on the second side, wherein when the first dielectric becomes exposed on the second side, the first dielectric covers the conductor on the second side so that the conductor is not exposed on the second side;
(d) after the first dielectric has been exposed on the second side, removing the material of the body and the first dielectric from the second side to expose the conductor in each of the openings, wherein the removing of the material of the body and the first dielectric comprises a process in which the removal rate of the first dielectric is lower than the removal rate of material of the body;
wherein the body comprises a transistor and/or a capacitor.
4 Assignments
0 Petitions
Accused Products
Abstract
To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 μm in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads. In some embodiments, the wafer etch and the fabrication of the additional dielectric are performed one after another by a plasma process while the wafer is held in a non-contact wafer holder. In some embodiments, the wafer is diced and the dice are tested before the etch. The etch and the deposition of the additional dielectric are performed on good dice only. In some embodiments, the dice are not used for vertical integration.
-
Citations
15 Claims
-
1. A method for fabricating an integrated circuit, the method comprising:
-
(a) providing a body having one or more openings in a first side;
(b) fabricating a first dielectric and a conductor in each of the one or more openings with the conductor in each of the openings being separated from the body by the first dielectric;
(c) removing material of the body from a second side of the body to expose the first dielectric on the second side, wherein when the first dielectric becomes exposed on the second side, the first dielectric covers the conductor on the second side so that the conductor is not exposed on the second side;
(d) after the first dielectric has been exposed on the second side, removing the material of the body and the first dielectric from the second side to expose the conductor in each of the openings, wherein the removing of the material of the body and the first dielectric comprises a process in which the removal rate of the first dielectric is lower than the removal rate of material of the body;
wherein the body comprises a transistor and/or a capacitor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
when the first dielectric is being removed in each of said openings to expose the conductor from the second side, the laterally surrounding semiconductor material of the body is being removed simultaneously and at a faster rate than the first dielectric. -
11. The method of claim 1 wherein removing the first dielectric at a lower rate than the material of the body improves electrical insulation between the conductor in each of said openings and the body.
-
12. The method of claim 1 further comprising attaching at least one conductor exposed on the second side to another conductor with solder, wherein the first dielectric protrudes from the second side around the exposed conductor and improves electrical insulation between the solder and the body.
-
13. The method of claim 1 wherein the operation (d) is an unmasked etch removing all of the material exposed on the second side at least until the conductor is exposed in each of the openings.
-
14. The method of claim 1 wherein after the conductor in each of the openings is exposed, said process continues to remove the material of the body and, at the same time, to remove the first dielectric at a lower rate than the material of the body.
-
15. The method of claim 1 wherein at the conclusion of the operation (d) the conductor protrudes from the second side at each of the openings.
-
Specification