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Vertical MOSFET with horizontally graded channel doping

  • US 6,740,920 B2
  • Filed: 03/11/2002
  • Issued: 05/25/2004
  • Est. Priority Date: 03/11/2002
  • Status: Expired due to Fees
First Claim
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1. A vertical transistor formed in well disposed in a semiconductor substrate, said well having a substantially uniform lateral well concentration of implanted well dopant parallel to a surface of said semiconductor, comprising:

  • a upper transistor electrode formed in a top level of said transistor;

    a lower transistor electrode formed in a lower level of said transistor;

    a gate dielectric extending downwardly from said upper transistor electrode toward said lower transistor electrode and abutting a transistor body formed in said semiconductor substrate;

    a threshold dopant distribution of dopant disposed in said transistor body, said threshold dopant distribution having a peak adjacent said gate dielectric and a lower value of threshold dopant concentration less than said lateral well concentration away from said gate dielectric; and

    a transistor gate disposed adjacent said gate dielectric on a side opposite said transistor body.

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