Vertical MOSFET with horizontally graded channel doping

• US 6,740,920 B2
• Filed: 03/11/2002
• Issued: 05/25/2004
• Est. Priority Date: 03/11/2002
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG), International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rengarajan, Rajesh, Lee, Kil-Ho, Chidambarrao, Dureseti, Mandelman, Jack A., McStay, Kevin
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): PHAM, HOAI V
• Application Number:
  US10/096,219
• Publication Number:
  US 20030168687A1
• Time in Patent Office: 806 Days
• Field of Search: 257/301, 257/302, 257/135, 257/263, 257/264, 257/328, 257/329, 257/330
• US Class Current: 257/302
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/39 the capacitor and the transistor being in a same trench

Abstract

Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low p-well concentration value. A preferred embodiment employs two body implants—an angled implant having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.

Claims

1. A vertical transistor formed in well disposed in a semiconductor substrate, said well having a substantially uniform lateral well concentration of implanted well dopant parallel to a surface of said semiconductor, comprising:

a upper transistor electrode formed in a top level of said transistor;

a lower transistor electrode formed in a lower level of said transistor;

a gate dielectric extending downwardly from said upper transistor electrode toward said lower transistor electrode and abutting a transistor body formed in said semiconductor substrate;

a threshold dopant distribution of dopant disposed in said transistor body, said threshold dopant distribution having a peak adjacent said gate dielectric and a lower value of threshold dopant concentration less than said lateral well concentration away from said gate dielectric; and

a transistor gate disposed adjacent said gate dielectric on a side opposite said transistor body.

2. A transistor according to claim 1, in which said threshold dopant distribution has a first lateral peak value in an upper portion of said transistor body and a second lateral peak value lower than said first lateral peak value in a lower portion of said body, whereby said concentration value of said threshold dopant distribution in said channel has a minimum value near said lower transistor electrode.

3. A transistor according to claim 2, in which said lateral peak value has a magnitude such that said transistor has a design threshold voltage.

4. A transistor according to claim 1, in which said threshold dopant distribution has a first lateral peak value in said peak, said first lateral peak value having a magnitude such that said transistor has a design threshold voltage.

5. A DRAM having an array of memory cells comprising a vertical transistor disposed above and connected to a capacitor, said vertical transistor being formed in a well disposed in a semiconductor substrate, said well having a substantially uniform lateral well concentration of implanted well dopant parallel to a surface of said semiconductor, said vertical transistor extending downwardly from an upper transistor electrode toward a capacitor electrode and comprising:

a lower transistor electrode formed in a lower level of said transistor and connected to said capacitor;

a gate dielectric extending downwardly from said upper transistor electrode toward said lower transistor electrode and abutting a transistor body formed in said semiconductor substrate;

a threshold dopant distribution of dopant disposed in said transistor body, said threshold dopant distribution having a peak adjacent said gate dielectric and a lower value of threshold dopant concentration less than said lateral well concentration away from said gate dielectric; and

a transistor gate disposed adjacent said gate dielectric on a side opposite said transistor body.

6. A DRAM according to claim 5, in which said threshold dopant distribution has a first lateral peak value in an upper portion of said transistor body and a second lateral peak value lower than said first lateral peak value in a lower portion of said body, whereby said concentration value of said threshold dopant distribution in said channel has a minimum value near said lower transistor electrode.