Semiconductor device and manufacturing method thereof
First Claim
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1. A semiconductor device, comprising:
- a first NMOS transistor and a first PMOS transistor provided respectively in a first NMOS region and a first PMOS region defined in a surface of a semiconductor substrate; and
a second NMOS transistor and a second PMOS transistor provided respectively in a second NMOS region and a second PMOS region defined in the surface of said semiconductor substrate;
said second NMOS transistor and said second PMOS transistor having higher operating voltages respectively than said first NMOS transistor and said first PMOS transistor, said second PMOS transistor being a buried-channel type MOS transistor in which a channel is formed in the inside of said semiconductor substrate, and said first NMOS transistor, said first PMOS transistor, and said second NMOS transistor being surface-channel type MOS transistors in which a channel is formed in the surface of said semiconductor substrate.
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Abstract
CMOS transistors which can satisfy demand for size reduction and demand for reliability and a manufacturing method thereof are provided. A buried-channel type PMOS transistor is provided only in a CMOS transistor (100B) designed for high voltage; surface-channel type NMOS transistors are formed in a low-voltage NMOS region (LNR) and a high-voltage NMOS region (HNR), and a surface-channel type PMOS transistor is formed in a low-voltage PMOS region (LPR).
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4 Claims
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1. A semiconductor device, comprising:
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a first NMOS transistor and a first PMOS transistor provided respectively in a first NMOS region and a first PMOS region defined in a surface of a semiconductor substrate; and
a second NMOS transistor and a second PMOS transistor provided respectively in a second NMOS region and a second PMOS region defined in the surface of said semiconductor substrate;
said second NMOS transistor and said second PMOS transistor having higher operating voltages respectively than said first NMOS transistor and said first PMOS transistor, said second PMOS transistor being a buried-channel type MOS transistor in which a channel is formed in the inside of said semiconductor substrate, and said first NMOS transistor, said first PMOS transistor, and said second NMOS transistor being surface-channel type MOS transistors in which a channel is formed in the surface of said semiconductor substrate. - View Dependent Claims (2, 3, 4)
a gate insulating film selectively provided on the surface of said semiconductor substrate in said second PMOS region, a gate electrode provided on said gate insulating film, a P-type impurity layer of a relatively low concentration provided in the surface of said semiconductor substrate right under said gate insulating film, and a pair of P-type source/drain layers provided in the surface of said semiconductor substrate outside of sides of said gate electrode and in contact with said impurity layer. -
3. The semiconductor device according to claim 2, wherein said pair of P-type source/drain layers comprise a pair of P-type extension layers extending from opposing ends and facing each other.
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4. The semiconductor device according to claim 2, wherein said gate electrode comprises an N-type impurity at a relatively high concentration.
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Specification