Dual-oxide transistors for the improvement of reliability and off-state leakage

• US 6,740,944 B1
• Filed: 07/03/2002
• Issued: 05/25/2004
• Est. Priority Date: 07/05/2001
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: McElheny, Peter John, Liu, Yowjuang (Bill)
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Huynh, Andy
• Application Number:
  US10/189,920
• Time in Patent Office: 692 Days
• Field of Search: 257/411, 257/336, 257/344, 257/408, 257/900, 257/297, 257/349, 257/304, 257/542, 257/620, 257/372-376, 257/503, 438/216, 438/261, 438/287, 438/591, 438/594, 438/981, 438/954
• US Class Current: 257/411
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

The invention provides a transistor having low leakage currents and methods of fabricating the transistor on a semiconductor substrate. The transistor has a gate and a nonuniform gate oxide under the gate.

Claims

1. A transistor fabricated on a semiconductor substrate, the transistor occupying an active area of the substrate, comprising:

a gate over the substrate and extending between two opposite sides of the active area;

a source region and a drain region in the substrate on opposite sides of the gate; and

a composite gate oxide layer having non-uniform thickness under the gate, the composite gate oxide layer having two end points near respective ones of the two opposite sides of the active area and a middle portion between the end portions, the two end portions being thicker than the middle portion.

2. The transistor of claim 1 wherein the composite oxide layer causes greater separation of the gate from the substrate near the two sides of the active area thereby reducing a fringe capacitance associated with the transistor.

3. The transistor of claim 2 wherein that the two end portions of the composite gate oxide extend beyond two sides of the gate.

4. The transistor of claim 2 wherein the transistor is adjacent to at least two isolation regions in the substrate so that the gate extends from one isolation region to another isolation region.

5. The transistor of claim 4 wherein the composite gate is oxide is thicker adjacent to the isolation regions thereby reducing leakage currents associated with the isolation regions.

6. The transistor of claim 1 wherein the composite gate oxide comprises a first oxide layer and a second oxide layer, the first oxide layer being nearly uniform under the gate and the second oxide layer covering a portion of the first oxide layer under the gate.

7. The transistor of claim 1 further comprising spacers adjacent the gate.

8. The transistor of claim 1 wherein doping concentrations in the source or drain region are lighter near the two opposite sides of the active area.

9. The transistor of claim 1 further comprising lightly doped drain regions adjacent the source and drain regions.

10. The transistor of claim 9 wherein doping concentrations in the lightly doped drain regions are lighter near the two opposite sides of the active area.

11. A device built on a substrate, comprising:

a gate over the substrate and extending between two isolation regions formed in the substrate;

source and drain diffusion regions in the substrate on two opposite sides of the gate and extending between the two isolation regions formed in the substrate; and

a gate oxide layer under the gate, the gate oxide layer having an end portion near at least one of the two isolation regions and a middle portion separated from the at least one of the two isolation regions by the end portion, the end portion being thicker than the middle portion.

12. The device of claim 11 wherein the thicker end portion serves to reduce a fringe capacitance associated with the device and to increase a speed of the device.

13. The device of claim 11 wherein the thicker end portion serves to minimize leakage currents associated with the formation of the isolation regions in the substrate.

14. The device of claim 11 wherein the device is part of an integrated circuit comprising high-voltage devices, and wherein the end portion of the gate oxide layer comprises a first oxide layer formed during the formation of an oxide layer in each of the high-voltage devices and a second oxide layer formed under the first oxide layer.

15. The device of claim 11 further comprising lightly doped drain regions between the gate and respective ones of the source and drain regions wherein the end portion extends beyond the two opposite sides of the gate to cover portions of the lightly doped drain regions.

16. A method for forming a transistor on a substrate, comprising

forming at least two isolation regions bordering two opposite sides of an active area of the transistor;

forming a composite gate oxide layer between the two isolation regions, the composite gate oxide layer comprising two end portions adjacent to respective ones of the isolation regions and a middle portion between the two end portions, the two end portions being thicker than the middle portion; and

forming a gate over the composite gate oxide layer and extending between the two isolation regions.

17. The method of claim 16 wherein forming the composite gate oxide layer comprises:

forming a first oxide layer between the two isolation regions;

etching the first oxide layer so that only small portions of the first oxide layer adjacent the two isolation regions remain after the etching; and

forming a second oxide layer having a uniform thickness between the two isolation regions, wherein the second oxide layer is under the first oxide layer in the end portions of the composite oxide layer.

18. The method of claim 17 wherein the transistor is part of an integrated circuit comprising high voltage devices and the first oxide layer is formed together with an oxide layer in each of the high voltage devices.

19. The method of claim 16 wherein the thicker end portions of the composite gate oxide layer extends beyond two opposite sides of the gate and the method further comprising:

forming lightly doped drain regions at the two sides of the gate by ion implants, wherein the ion implants are partially blocked by the thicker end portions of the composite gate oxide layer resulting in lower dopant concentrations in portions of the lightly doped drain regions near the end portions of the composite gate oxide layer.

20. The method of claim 19, further comprising:

forming source and drain regions at the two opposite sides of the gate.