Method and system for detecting an arc condition

• US 6,741,092 B2
• Filed: 12/28/2001
• Issued: 05/25/2004
• Est. Priority Date: 12/28/2001
• Status: Expired due to Fees

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Juergen Zschiegner, Stefan Jan, Eldridge, Benjamin N.
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Nguyen, Jimmy
• Application Number:
  US10/035,364
• Publication Number:
  US 20030122568A1
• Time in Patent Office: 879 Days
• Field of Search: 324/754, 324/765, 324/158.1, 324/758, 324/72.5, 324/755, 324/761, 324/757, 438/17, 438/18, 438/19, 204/192.13
• US Class Current: 324/754.07
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00

Abstract

A method and apparatus for detecting an arc condition in a semiconductor test system is disclosed. While probes in a semiconductor test system are being moved into or out of contact with a semiconductor wafer, the voltage level of power supplied to selected ones of the probes is monitored. If the voltage level of the power exceeds a level that could cause an arc between the probes and the semiconductor wafer while the wafer is being moved, an indication is generated that an arc condition has been detected.

Claims

1. An apparatus comprising:

a comparator having an input connected to a reference voltage and another input connected to a power source to a test probe for contacting a semiconductor wafer;

a latch having an input connected to an output of said comparator;

enabling means for enabling said latch only in connection with a move of said wafer with respect to said probe; and

signaling means for signaling an arc condition if said output of said latch indicates that said output of said comparator was triggered while said latch is enabled.

2. The apparatus of claim 1, wherein said reference voltage corresponds to a voltage level sufficient to cause an arc between said probe and said wafer.

3. The apparatus of claim 1, wherein said enabling means enables said latch prior to said move of said wafer and disables said latch after completion of said move.

4. The apparatus of claim 1, wherein said signaling means activates an indicator.

5. The apparatus of claim 1, wherein said signaling means lights a light.

6. The apparatus of claim 1, wherein said signaling means sends a message.

7. The apparatus of claim 1 further comprising:

a plurality of said comparators, each having an input connected to said reference voltage and another input connected to a power source to one of a plurality of said test probes; and

a plurality of said latches, each having an input connected to an output of one of said comparators.

8. The apparatus of claim 1, wherein said another of said inputs of said comparator is indirectly connected to said power source to said test probe.

9. The apparatus of claim 8, wherein said another of said inputs of said comparator is capacitively connected to said power source to said test probe.

10. The apparatus of claim 1, wherein

said test probe is disposed on a probe card assembly, and

said comparator and said latch are disposed on a substrate that is pluggable into a socket on said probe card assembly.

21. The method of claim 1 further comprising:

monitoring voltages on a plurality of power sources to a plurality of said probes; and

if at least one of said voltages exceeds a predetermined threshold during said move of said stage, signaling an arc condition.

11. An apparatus for testing a semiconductor wafer, said apparatus comprising:

moving means for moving said wafer into and out of contact with probes of a probe card assembly;

monitoring means for monitoring a voltage level of power supplied to one of said probes;

signaling means for signaling an arc condition if said voltage exceeds a predetermined threshold during a move of said wafer.

12. The method of claim 11, wherein:

said monitoring means further monitors voltage levels of power supplied to a plurality of said probes; and

said signaling means further signals an arc condition if said voltage of power supplied to at least one of said probes exceeds said predetermined threshold.

13. A method for use in a system for testing a semiconductor wafer, said system comprising a stage for moving said wafer into and out of contact with a plurality of probes, said method comprising:

monitoring a voltage on a power source to one of said probes; and

if said voltage exceeds a predetermined threshold during a move of said stage, signaling an arc condition.

14. The method of claim 13, wherein said monitoring comprises comparing said voltage on said power source to a reference voltage.

15. The method of claim 14, wherein said signaling an arc condition comprises enabling an output of a result of said comparing during said move of said stage.

16. The method of claim 15, wherein said enabling comprises:

receiving an indication that a move of said stage is to take place; and

enabling said output of said result in response to said indication that a move of said stage is to take place.

17. The method of claim 16, wherein said enabling further comprises:

receiving an indication that said move has been completed; and

disabling said output of said result in response to said indication that said move has been completed.

18. The method of claim 13, wherein said signaling an arc condition comprises activating an indicator.

19. The method of claim 13, wherein said signaling an arc condition comprises lighting a light.

20. The method of claim 13, wherein said signaling an arc condition comprises sending a message.