Transistor driver circuit

• US 6,741,099 B1
• Filed: 01/31/2003
• Issued: 05/25/2004
• Est. Priority Date: 01/31/2003
• Status: Expired due to Term

• Current Assignee: Bel Power Solutions Inc.
• Original Assignee: Power One Ltd (ABB Limited)
• Inventors: Krugly, Simon
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Nguyen, Khai M.
• Application Number:
  US10/357,313
• Time in Patent Office: 480 Days
• Field of Search: 326/17, 326/26, 326/27, 326/82, 326/83, 326/86, 326/112, 326/119
• US Class Current: 326/82
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 2017/6875 using self-conductive, depletion FETs

Abstract

The invention is related to methods and apparatus for driving transistors. One embodiment includes a driver circuit that can drive power transistors at relatively high switching speeds, which can advantageously decrease the size of associated electronics systems that use the driver circuit and power transistors. Embodiments of the invention can drive a switching device that needs a negative voltage bias in order to be shut off. For example, the switching device can correspond to a junction field effect transistor (JFET). Advantageously, one embodiment of the invention can drive such switching devices on and off from a single positive voltage supply.

Claims

1. A gate drive circuit for an N-Channel junction field effect transistor (JFET), the gate drive circuit comprising:

a P-Channel metal oxide semiconductor field effect transistor (P-Ch MOSFET) with a gate, a source, and a drain, where the gate of the P-Ch MOSFET is configured to receive a control signal for the gate drive circuit, and where the source of the P-Ch MOSFET is configured to couple to a positive voltage bias;

an N-Channel metal oxide semiconductor field effect transistor (N-Ch MOSFET) with a gate, a source, and a drain, where the gate of the N-Ch MOSFET is coupled to the gate of the P-Ch MOSFET such that the P-Ch MOSFET and the N-Ch MOSFET are responsive to the control signal, where the source of the N-Ch MOSFET is configured to couple to ground;

a diode with an anode and a cathode, where the anode is coupled to the drain of the P-Ch MOSFET and the cathode is coupled to the drain of the N-Ch MOSFET;

a resistor with a first terminal and a second terminal, where the first terminal of the resistor is coupled to the drain of the P-Ch MOSFET; and

a capacitor with a first terminal and a second terminal, where the first terminal of the capacitor is coupled to the drain of the N-Ch MOSFET, and where the second terminal of the capacitor is coupled to the second terminal of the resistor and is provided as an output of the gate drive circuit.

2. The gate drive circuit as defined in claim 1, further comprising a buffer circuit configured to generate the control signal input.

3. The gate drive circuit as defined in claim 1, where the control signal input swings from approximately ground to approximately the positive voltage bias.

4. A power supply embodying the gate drive circuit of claim 1.

5. A transistor input drive circuit comprising:

a first switching device with a control terminal, a first switching terminal, and a second switching terminal, where the control terminal of the first switching device is configured to receive a control signal for the transistor input drive circuit such that the first switching device is conductive from the first switching terminal to the second switching terminal in a first state of the control signal and is not conductive from the first switching terminal to the second switching terminal in a second state of the control signal, and where the first switching terminal of the first switching device is configured to couple to a first voltage reference;

a second switching device with a control terminal, a first switching terminal, and a second switching terminal, where the control terminal of the second switching device is coupled to the control signal such that the second switching device is not conductive from the first switching terminal to the second switching terminal in the first state of the control signal and is conductive from the first switching terminal to the second switching terminal in the second state of the control signal, where the first switching terminal of the second switching device is configured to couple to a second voltage reference;

a rectifying device with at least a first terminal and a second terminal, where a first terminal of the rectifying device is coupled to a source of supply for the first voltage reference at least during the first state of the control signal, where the rectifying device is configured to provide conduction from the first voltage reference to the second terminal during the first state but not during the second state of the control signal, where the second terminal is coupled to the second switching terminal of the second switching device;

a resistor with a first terminal and a second terminal, where the first terminal of the resistor is coupled to the second switching terminal of the second switching device; and

a capacitor with a first terminal and a second terminal, where the first terminal of the capacitor is coupled to the second switching terminal of the second switching device, and where the second terminal of the capacitor is coupled to the second terminal of the resistor and is provided as an output of the gate drive circuit.

6. The transistor input drive circuit as defined in claim 5, wherein the first voltage reference is a positive voltage reference, and the second voltage reference is ground.

7. The gate drive circuit as defined in claim 5, further comprising a buffer circuit configured to generate the control signal, where the buffer circuit is configured to provide a low impedance to the first voltage reference in the second state and a low impedance to the second voltage reference in the first state in response to an input signal to the buffer circuit.

8. The transistor input drive circuit as defined in claim 5, wherein the first switching device is a P-Channel metal oxide semiconductor field effect transistor (P-Ch MOSFET), where the control terminal of the first switching device corresponds to a gate of the P-Ch MOSFET, where the first switching terminal of the first switching device corresponds to a source of the P-Ch MOSFET, and where the second switching terminal of the first switching device corresponds to a drain of the P-Ch MOSFET.

9. The transistor input drive circuit as defined in claim 5, wherein the second switching device is an N-Channel metal oxide semiconductor field effect transistor (N-Ch MOSFET), where the control terminal of the second switching device corresponds to a gate of the N-Ch MOSFET, where the first switching terminal of the second switching device corresponds to a source of the N-Ch MOSFET, and where the second switching terminal of the second switching device corresponds to a drain of the N-Ch MOSFET.

10. The transistor input drive circuit as defined in claim 5, wherein the rectifying device corresponds to a diode with an anode and a cathode, where the first terminal of the rectifying device corresponds to the anode of the diode, where the second terminal of the rectifying device corresponds to the cathode of the diode, and where the anode of the diode is coupled to the second switching terminal of the first switching device such that the first terminal of the rectifying device is coupled to the source of the first voltage reference via the first switching device.

11. The transistor input drive circuit as defined in claim 5, wherein the rectifying device corresponds to a P-Channel metal oxide semiconductor field effect transistor (P-Ch MOSFET) with a gate, a source, and a drain, where the source of the P-Ch MOSFET corresponds to the first terminal of the rectifying device and is coupled to the first voltage reference, where the gate is coupled to the control signal such that the rectifying device is configured to provide conduction from the first voltage reference to the second terminal during the first state, but not during the second state of the control signal, and where the drain corresponds to the second terminal of the rectifying device.

12. The transistor input drive circuit as defined in claim 5, wherein a transistor that is driven by the transistor input drive circuit corresponds to an N-Channel vertical power JFET.

13. A power supply embodying the gate drive circuit of claim 5.

14. A transistor input drive circuit comprising:

an input for a control signal;

an output for a drive signal;

a first switching circuit coupled to the input, where the first switching circuit is configured to switch on a positive bias to the output in response to a first state of the control signal; and

a second switching circuit coupled to the input, where the second switching circuit is configured to provide a negative voltage on the output in response to a second state of the control signal.

15. The transistor input drive circuit as defined in claim 14, wherein the second switching circuit is further configured to provide the negative voltage without a negative voltage power supply bias.

16. The transistor input drive circuit as defined in claim 14, wherein the second switching circuit is further configured to provide the negative voltage without a negative voltage power supply bias and without transformer coupling.

17. The transistor input drive circuit as defined in claim 14, wherein the transistor input drive circuit is configured to operate from a single positive voltage power supply bias.

18. The transistor input drive circuit as defined in claim 14, further comprising an input buffer circuit disposed between the input and the first switching circuit and between the input and the second switching circuit, where the input buffer circuit is configured to provide a high input impedance to the input and is configured to provide a low output impedance to the first switching circuit and to the second switching circuit.

19. A power supply embodying the gate drive circuit of claim 14.

20. A circuit comprising:

an input for a control signal;

a first switching circuit coupled to the input, where the first switching circuit is configured to switch on a positive bias to a drive output in response to a first state of the control signal;

a second switching circuit coupled to the input, where the second switching circuit is configured to provide a negative voltage on the drive output in response to a second state of the control signal; and

a power junction field effect transistor (power JFET) with a gate, a source, and a drain, where the gate is coupled to the drive output, where the source is coupled to a voltage reference, and the drain is configured to be coupled to a load.

21. The circuit as defined in claim 20, wherein the voltage reference is ground.

22. The circuit as defined in claim 20, wherein the second switching circuit is further configured to provide the negative voltage without a negative voltage power supply bias.

23. A power supply embodying the circuit of claim 20.

24. A transistor input drive circuit comprising:

means for receiving a control signal as an input, where the control signal has a first state and a second state;

means for providing a positive bias on an output of the transistor drive circuit in response to the first state of the control signal;

a capacitor with a first terminal and a second terminal, where the second terminal is coupled to the output of the transistor input drive circuit;

means for charging the capacitor by coupling a positive voltage reference to the first terminal of the capacitor in response to the first state of the control signal; and

means for switching the first terminal of the capacitor to a second voltage reference that is lower in voltage than the positive voltage reference to provide a negative bias on the output of the transistor drive circuit in response to the second state of the control signal.

25. The transistor input drive circuit as defined in claim 24, wherein the second voltage reference is ground.

26. The transistor input drive circuit as defined in claim 24, wherein the means for charging the capacitor charges the capacitor through a current flow path that includes an input of a device coupled to the output of the transistor input drive circuit.

27. A method of driving a power transistor, the method comprising:

receiving a control signal as an input, where the control signal has a first state and a second state;

providing a positive bias to an input of the power transistor in response to the first state, where the positive bias can drive the power transistor to an “

on”

state;

charging a capacitor in response to the first state, where a charging current for the capacitor flows into a first terminal of the capacitor and flows through a path including the input of the power transistor;

disabling the positive bias in response to a second state; and

switching the first terminal of the capacitor to a voltage reference in response to the second state such that a second terminal of the capacitor provides a negative voltage as an output to the input of the power transistor, where the negative voltage can drive the power transistor to an “

off”

state.

28. The method as defined in claim 27, where the voltage reference is ground.

29. The method as defined in claim 27, further comprising buffering the control signal.

30. The method as defined in claim 27, wherein the positive bias is provided to the power transistor by switching voltage to a resistor that is coupled to the input of the power transistor.

31. The method as defined in claim 27, wherein the power transistor is an N-Channel vertical power junction field effect transistor (JFET).