Low glitch current steering digital to analog converter and method

• US 6,741,195 B1
• Filed: 12/11/2002
• Issued: 05/25/2004
• Est. Priority Date: 12/11/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cho, Kwang-Bo
• Primary Examiner(s): Williams, Howard L
• Application Number:
  US10/317,678
• Time in Patent Office: 531 Days
• Field of Search: 341/133, 341/135, 341/136, 341/144, 323/315, 323/316
• US Class Current: 341/136
• CPC Class Codes: H03M 1/0872 by disabling changes in the output during the transitions, e.g. by holding or latching
• CPC Class Codes: H03M 1/742 using current sources as quantisation value generators

Abstract

A current steered digital to analog converter (DAC) circuit includes a reference input transistor, a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output and an output current mirror having an input coupled to the combined current source output. The output current mirror provides current gain to enable the DAC circuit to provide the required output current magnitude, while at the same time, enabling the DAC itself to operate with a smaller reference current into the DAC. The output current mirror may advantageously be either a regulated cascode current mirror or a high-swing cascode current mirror.

Claims

1. A DAC circuit comprising:

a reference input transistor;

a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output; and

an output current mirror having an input coupled to the combined current source output, the output mirror comprising;

an input transistor having a first gate electrode, a first drain coupled to the first gate electrode, and a first source;

a first output transistor having a second gate electrode coupled to the first gate electrode and to the combined current source output, a second drain, and a second source coupled to the first source, the first output transistor being scaled to pass an output current between the second drain and second source that is a predetermined proportion of an input current passed between the first drain and the first source;

a third transistor scaled to match the input transistor and having a third gate electrode coupled to the first gate electrode, a third drain, and a third source coupled to the first source;

a fourth transistor having a fourth gate electrode, a fourth drain coupled to the third drain, and a fourth source;

a fifth transistor scaled to match the fourth transistor and having a fifth gate electrode coupled to the fourth gate electrode and to the fourth drain, a fifth drain and a fifth source coupled to the fourth source;

a sixth transistor having a sixth gate electrode coupled to the second drain, a sixth drain coupled to the fifth drain and a sixth source coupled to the second source;

a second output transistor having a seventh gate electrode coupled to the sixth drain, a seventh drain and a seventh source coupled to the second drain.

2. The circuit of claim 1, wherein the predetermined proportion is greater than unity.

3. A DAC circuit comprising:

a reference input transistor;

a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output; and

an output current mirror having an input coupled to the combined current source output, the output mirror comprising;

a first input transistor having a first gate electrode, a first drain and a first source; and

a first output transistor having a second gate electrode, a second drain and a second source, the first and second gate electrodes being coupled together and to the combined current source output, the first and second sources being coupled together, the first output transistor being scaled to pass an output current between the second drain and second source that is a predetermined proportion of an input current passed between the first drain and the first source;

a third transistor scaled to match the first input transistor and having a third gate electrode coupled to the first gate electrode, a third drain and a third source coupled to the first sources;

a fourth transistor having a fourth gate electrode, a fourth drain coupled to the third drain and a fourth source;

a fifth transistor scaled to match the fourth transistor and having a fifth gate electrode coupled to the fourth gate electrode and to the fourth drain, a fifth drain and a fifth source coupled to the fourth source;

a sixth transistor having a sixth gate electrode coupled to the fifth drain, a sixth drain coupled to the fifth drain and a sixth source coupled to the second source;

a second output transistor having a seventh gate electrode coupled to the sixth gate electrode, a seventh drain and a seventh source coupled to the second drain; and

a second input transistor having an eighth gate electrode coupled to the sixth and seventh gate electrodes, an eighth drain coupled to the first gate electrode and an eighth source coupled to the first drain.

4. A DAC circuit comprising:

a reference input transistor;

a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output; and

an output current mirror having an input coupled to the combined current source output, the output current mirror comprising;

one of a regulated cascode current mirror and a high-swing cascode current mirror, the output current mirror including an input transistor having a first gate electrode, a first drain and a first source, the output current mirror further including an output transistor having a second gate electrode coupled to the first gate electrode and to the combined current source output, a second drain and a second source coupled to the first source, the output transistor being scaled to pass an output current between the second drain and second source that is a predetermined proportion greater than one of an input current passed between the first drain and the first source;

a third transistor scaled to match the input transistor and having a third gate electrode coupled to the first gate electrode, a third drain and a third source coupled to the first source;

a fourth transistor having a fourth gate electrode, a fourth drain coupled to the third drain and a fourth source;

a fifth transistor scaled to match the fourth transistor and having a fifth gate electrode coupled to the fourth gate electrode, a fifth drain and a fifth source, the fifth gate electrode being further coupled to the fourth drain;

a sixth transistor having a sixth gate electrode, a sixth drain coupled to the fifth drain and a sixth source coupled to the second source; and

another output transistor having a seventh gate electrode, a seventh drain and a seventh source coupled to the second drain.

5. A DAC circuit comprising:

a reference input transistor;

a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output; and

an output current mirror having an input coupled to the combined current source output, the output current mirror comprising;

a high-swing cascode current mirror including a first input transistor having a first gate electrode, a first drain and a first source, the output current mirror further including a first output transistor having a second gate electrode coupled to the first gate electrode and to the combined current source output, a second drain and a second source coupled to the first source, the first output transistor being scaled to pass an output current between the second drain and second source that is a predetermined proportion greater than one of an input current passed between the first drain and the first source;

a third transistor scaled to match the first input transistor and having a third gate electrode coupled to the first gate electrode, a third drain and a third source coupled to the first source;

a fourth transistor having a fourth gate electrode, a fourth drain coupled to the third drain and a fourth source;

a fifth transistor scaled to match the fourth transistor and having a fifth gate electrode coupled to the fourth gate electrode, a fifth drain and a fifth source, the fifth gate electrode being further coupled to the fourth drain;

a sixth transistor having a sixth gate electrode coupled to the fifth drain, a sixth drain coupled to the fifth drain and a sixth source coupled to the second source;

a second output transistor having a seventh gate electrode coupled to the sixth gate electrode, a seventh drain and a seventh source coupled to the second drain; and

a second input transistor having an eighth gate electrode coupled to the sixth and seventh gate electrodes, an eighth drain and an eighth source coupled to the first drain.

6. A DAC circuit comprising:

a reference input transistor;

a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output; and

an output current mirror having an input coupled to the combined current source output, the output current mirror comprising;

an input transistor having a first gate electrode, a first drain and a first source;

a first output transistor having a second gate electrode coupled to the first gate electrode, a second drain and a second source coupled to the first source;

a second output transistor having a third gate electrode coupled to the first and second gate electrodes and to the combined current source output, a third drain and a third source coupled to the first and second sources;

a first switch transistor having a fourth gate electrode, a fourth drain and a fourth source coupled to the second drain; and

a second switch transistor having a fifth gate electrode, a fifth drain coupled to the fourth drain and a fifth source coupled to the third drain.

7. A DAC circuit comprising:

a reference input transistor;

a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output; and

an output current mirror having an input coupled to the combined current source output; and

an input current mirror comprising;

an input transistor having a first gate electrode, a first drain and a first source;

a first output transistor having a second gate electrode coupled to the first gate electrode and to the first drain, a second drain and a second source coupled to the first source;

a second output transistor having a third gate electrode coupled to the first and second gate electrodes and to the first drain, a third drain and a third source coupled to the first and second sources;

a first switch transistor having a fourth gate electrode, a fourth drain and a fourth source coupled to the second drain; and

a second switch transistor having a fifth gate electrode, a fifth drain coupled to the fourth drain and a fifth source coupled to the third drain.

8. The circuit of claim 7, wherein the output current mirror further comprises:

an input transistor having a sixth gate electrode, a sixth drain and a sixth source;

a first output transistor having a seventh gate electrode coupled to the sixth gate electrode and to the combined current source output, a seventh drain and a seventh source coupled to the sixth source;

a second output transistor having an eighth gate electrode coupled to the sixth and seventh gate electrodes and to the combined current source output, an eighth drain and an eighth source coupled to the sixth and seventh sources;

a first switch transistor having a ninth gate electrode, a ninth drain and a ninth source coupled to the seventh drain; and

a second switch transistor having a tenth gate electrode, a tenth drain coupled to the ninth drain and a tenth source coupled to the eighth drain.

9. A sensor comprising at least one DAC circuit, the at least one DAC circuit comprising a reference input transistor, a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output, and an output current mirror having an input coupled to the combined current source output, the output current mirror comprising:

an input transistor having a first gate electrode, a first drain coupled to the first gate electrode, and a first source;

an first output transistor having a second gate electrode, a second drain and a second source, the first and second gate electrodes being coupled together and to the combined current source output, the first and second sources being coupled together, the first output transistor being scaled to pass an output current between the second drain and second source that is a predetermined proportion of an input current passed between the first drain and the first source;

a third transistor scaled to match the input transistor and having a third gate electrode coupled to the first gate electrode, a third drain and a third source coupled to the first source;

a fourth transistor having a fourth gate electrode, a fourth drain coupled to the third drain and a fourth source;

a fifth transistor scaled to match the fourth transistor and having a fifth gate electrode coupled to the fourth gate electrode and coupled to the fourth drain, a fifth drain and a fifth source;

a sixth transistor having a sixth gate electrode coupled to the second drain, a sixth drain coupled to the fifth drain and a sixth source coupled to the second source; and

a second output transistor having a seventh gate electrode coupled to the sixth drain, a seventh drain and a seventh source coupled to the second drain.

10. A sensor comprising at least one DAC circuit, the at least one DAC circuit comprising a reference input transistor, a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output, and an output current mirror having an input coupled to the combined current source output, the output current mirror comprising:

a first input transistor having a first gate electrode, a first drain and a first source;

an first output transistor having a second gate electrode, a second drain and a second source, the first and second gate electrodes being coupled together and to the combined current source output, the first and second sources being coupled together, the first output transistor being scaled to pass an output current between the second drain and second source that is a predetermined proportion of an input current passed between the first drain and the first source;

a third transistor scaled to match the first input transistor and having a third gate electrode coupled to the first gate electrode, a third drain and a third source coupled to the first source;

a fourth transistor having a fourth gate electrode, a fourth drain coupled to the third drain and a fourth source;

a fifth transistor scaled to match the fourth transistor and having a fifth gate electrode coupled to the fourth gate electrode and coupled to the fourth drain, a fifth drain and a fifth source;

a sixth transistor having a sixth gate electrode, a sixth drain coupled to the fifth drain and a sixth source coupled to the second source; and

a second output transistor having a seventh gate electrode, a seventh drain and a seventh source coupled to the second drain;

a second input transistor having an eighth gate electrode, an eighth drain coupled to the first gate electrode and an eighth source coupled to the first drain, the sixth gate electrode being coupled to the fifth drain, the sixth, seventh and eighth gate electrodes being coupled together.

11. A camera comprising a sensor including at least one DAC circuit, the at least one DAC circuit comprising a reference input transistor, a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output, and an output current mirror having an input coupled to the combined current source output, the output current mirror comprising:

an input transistor having a first gate electrode, a first drain coupled to the first gate electrode, and a first source;

a first output transistor having a second gate electrode, a second drain and a second source, the first and second gate electrodes being coupled together and to the combined current source output, the first and second sources being coupled together, the first output transistor being scaled to pass an output current between the second drain and second source that is a predetermined proportion of an input current passed between the first drain and the first source;

a third transistor scaled to match the input transistor and having a third gate electrode coupled to the first gate electrode, a third drain and a third source coupled to the first source;

a fourth transistor having a fourth gate electrode, a fourth drain coupled to the third drain and a fourth source;

a fifth transistor scaled to match the fourth transistor and having a fifth gate electrode, a fifth drain and a fifth source, the fourth and fifth gate electrodes being coupled together and to the fourth drain;

a sixth transistor having a sixth gate electrode coupled to the second drain, a sixth drain coupled to the fifth drain and a sixth source coupled to the second source; and

a second output transistor having a seventh gate electrode coupled to the sixth drain, a seventh drain and a seventh source coupled to the second drain.

12. A camera comprising a sensor including at least one DAC circuit, the at least one DAC circuit comprising a reference input transistor, a plurality of current steered current sources each coupled to the reference input transistor and configured to provide a combined current source output, and an output current mirror having an input coupled to the combined current source output, the output current mirror comprising:

a first input transistor having a first gate electrode, a first drain and a first source;

a first output transistor having a second gate electrode, a second drain and a second source, the first and second gate electrodes being coupled together and to the combined current source output, the first and second sources being coupled together, the first output transistor being scaled to pass an output current between the second drain and second source that is a predetermined proportion of an input current passed between the first drain and the first source;

a third transistor scaled to match the first input transistor and having a third gate electrode coupled to the first gate electrode, a third drain and a third source coupled to the first source;

a fourth transistor having a fourth gate electrode, a fourth drain coupled to the third drain and a fourth source;

a fifth transistor scaled to match the fourth transistor and having a fifth gate electrode, a fifth drain and a fifth source, the fourth and fifth gate electrodes being coupled together and to the fourth drain;

a sixth transistor having a sixth gate electrode, a sixth drain coupled to the fifth drain and a sixth source coupled to the second source;

a second output transistor having a seventh gate electrode, a seventh drain and a seventh source coupled to the second drain; and

a second input transistor having an eighth gate electrode, an eighth drain coupled to the first gate electrode and an eighth source coupled to the first drain, the sixth gate electrode being coupled to the fifth drain, the sixth, seventh and eighth gate electrodes are coupled together.

13. A method comprising:

applying a reference current to a reference input transistor that is coupled to a plurality of current steered current sources;

converting plural digital signals into a combined current source output from the plurality of current steered current sources based on the reference current;

coupling an input of an output current mirror to the combined current source output; and

providing a circuit output current at an output of the output current mirror, a magnitude of the circuit output current being greater than a magnitude of the combined current source output, the circuit output current being provided by controlling output current mirror switches to selectively control an output current mirror gain ratio defined as the magnitude of the circuit output current divided by the magnitude of the combined current source output so that the output current mirror gain ratio is one of a first predetermined output gain ratio and a second predetermined output gain ratio, the first predetermined output gain ratio being different than the second predetermined output gain ratio.

14. A method comprising:

applying a reference current to a reference input transistor that is coupled to a plurality of current steered current sources;

converting plural digital signals into a combined current source output from the plurality of current steered current sources based on the reference current by providing an input current mirror output current from an input current mirror portion of a current steered DAC by controlling input current mirror switches to selectively control the input current mirror output current to be one of a first predetermined output current and a second predetermined output current, the first predetermined output current being different than the second predetermined output current;

coupling an input of an output current mirror to the combined current source output; and

providing a circuit output current at an output of the output current mirror, a magnitude of the circuit output current being greater than a magnitude of the combined current source output.

15. The method of claim 14, wherein:

an output current mirror gain ratio is defined by a magnitude of the circuit output current divided by the magnitude of the combined current source output; and

the providing of a circuit output current includes controlling output current mirror switches to selectively control the output current mirror gain ratio to be one of a first predetermined output gain ratio and a second predetermined output gain ratio, the first predetermined output gain ratio being different than the second predetermined output gain ratio.

16. A method comprising:

applying a reference current to a reference input transistor that is coupled to a plurality of current steered current sources;

converting plural digital signals into a combined current source output from the plurality of current steered current sources based on the reference current;

coupling an input of an output current mirror to the combined current source output; and

providing a circuit output current at an output of the output current mirror having a magnitude that is at least ten times greater than a magnitude of the combined current source output.

17. A method comprising:

applying a reference current to a reference input transistor that is coupled to a plurality of current steered current sources;

converting plural digital signals into a combined current source output from the plurality of current steered current sources based on the reference current;

coupling an input of an output current mirror to the combined current source output; and

providing a circuit output current at an output of the output current mirror having a magnitude that is at least one hundred times greater than a magnitude of the combined current source output.

18. A method comprising:

applying a reference current to a reference input transistor that is coupled to a plurality of current steered current sources;

converting plural digital signals into a combined current source output from the plurality of current steered current sources based on the reference current;

coupling an input of an output current mirror to the combined current source output; and

providing a circuit output current at an output of the output current mirror having a magnitude that is at least one thousand times greater than a magnitude of the combined current source output.