Predictive optimizer for DRAM memory

• US 6,741,256 B2
• Filed: 08/27/2001
• Issued: 05/25/2004
• Est. Priority Date: 08/27/2001
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Emberling, Brian D.
• Primary Examiner(s): Tung, Kee M.
• Assistant Examiner(s): Monestime, Mackly
• Application Number:
  US09/940,233
• Publication Number:
  US 20030038810A1
• Time in Patent Office: 1,002 Days
• Field of Search: 345/557, 345/558, 345/540, 711/157, 711/158, 710/112, 710/113, 710/114
• US Class Current: 345/540
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/122 Tiling
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G09G 5/026 Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A predictive optimizing unit for use with an interleaved memory and suitable for use in a computer graphics system is described. The unit maintains a queue of pending requests for data from the memory, and prioritizes precharging and activating interleaves with pending requests. Interleaves which are in a ready state may be accessed independently of the precharging and activation of non-ready interleaves.

Claims

1. A graphics system comprising:

a memory configured to receive and store graphics data, wherein the memory is subdivided into banks;

a FIFO memory configured to buffer requests for the graphics data stored in the memory;

a set of scoreboard registers, wherein the scoreboard registers are configured to store status information representative of the state of the banks of memory, and wherein each scoreboard register is associated with one bank of the memory; and

a prefetch logic unit connected to the FIFO, the scoreboard registers, and the memory, wherein the prefetch logic unit is configured to examine pending requests buffered in the FIFO, wherein the prefetch logic unit issues commands and addresses to the memory according to the pending requests buffered in the FIFO and the status information stored in the scoreboard registers.

2. The graphics system of claim 1, wherein the graphics data comprises texels, wherein the texels are picture elements of a texture image.

3. The graphics system of claim 1, wherein the requests for graphics data comprise base addresses of the graphics data.

4. The graphics system of claim 1, wherein the FIFO memory includes parallel outputs, wherein each parallel output conveys the contents of one entry in the FIFO to the prefetch logic unit, and wherein the number of parallel outputs is equal to the number of entries in the FIFO.

5. The graphics system of claim 4, wherein the banks of memory are further subdivided into logical pages, and wherein the FIFO parallel outputs are configured to output page addresses based on the requests for graphics data.

6. The graphics system of claim 1, wherein the scoreboard registers are further configured to indicate three states, wherein a first state indicates that the associated bank of the memory is precharging, wherein a second state indicates that the associated bank of the memory is precharged, and wherein a third state indicates that the associated bank of the memory is active.

7. The graphics system of claim 6, wherein each scoreboard register further comprises a precharging timer, wherein each precharging timer modifies the associated state of the memory stored in the scoreboard register to indicate that the associated bank of the memory is precharged in response to the timer reaching a terminal count.

8. The graphics system of claim 1, further comprising a refresh timer connected to the prefetch logic unit and the scoreboard registers, wherein the refresh timer repeatedly issues requests to initiate memory refresh cycles, and wherein the status information stored in the scoreboard registers is modified as part of the requests to initiate memory refresh cycles.

9. The graphics system of claim 1, wherein the prefetch logic unit tests the banks of memory against the buffered requests for graphics data, wherein the prefetch logic unit issues precharge and activate commands to a bank of memory in response to identifying the bank of memory as not ready to respond to a pending request for graphics data.

10. A graphics system comprising;

an interleaved memory configured to receive, store and retrieve arrays of image data, wherein each interleave of the interleaved memory is configured to receive commands independent of the other interleaves;

a request queue configured to store pending requests for arrays of image data;

a set of status registers configured to store status information indicative of the status of each interleave of the interleaved memory; and

a memory controller connected to the request queue, the status registers, and the interleaved memory and configured to convey requests for arrays of image data to the interleaved memory, and wherein the memory controller is further configured to make ready for access each interleave of the interleaved memory according to pending requests stored in the request queue.

11. The graphics system of claim 10, wherein the arrays of image data have fixed dimensions, and wherein individual elements in an array of image data are identified by the row and column in which they reside, and wherein each element in an array of image data is associated with a single interleave of the interleaved memory.

12. The graphics system of claim 10, wherein the interleaved memory comprises SDRAM devices.

13. The graphics system of claim 10, wherein the request queue comprises:

a serial input port configured to receive addresses and store them in a set of memory locations, wherein the addresses are representative of requests for arrays of image data;

a serial output port configured to sequentially output the addresses stored in the set of memory locations in response to a command from the memory controller, wherein the serial output port is further configured to output the least recently stored address in the set of memory locations, and wherein an address is removed from the set of memory locations as a part of conveying the address to the serial output port;

a parallel output port configured to output a partial address for each of the interleaves in the interleaved memory, wherein the partial address represents the least recently stored address in the set of memory locations which refers to the associated interleave, and wherein the partial address further represents a row of image data within the associated interleave.

14. The graphics system of claim 10, wherein the status information stored in the set of status registers comprises:

a current state indicator, wherein the current state indicator may assume a first value indicating that the associated interleave of the interleaved memory is in a precharging state, wherein the current state indicator may assume a second value indicating that the associated interleave of the interleaved memory is in a precharged state, and wherein the current state indicator may assume a third value indicating that the associated interleave of the interleaved memory is in an active state;

an active row indicator configured to store a row address if the current state indicator indicates that the associated interleave of the interleaved memory is in an active state;

a precharging timer configured to indicate the termination of a precharging cycle in the associated interleave of the interleaved memory; and

an activate timer configured to indicate the termination of an activation cycle in the associated interleave of the interleaved memory.

15. The graphics system of claim 14, wherein the precharging timer is further configured to begin a countdown cycle as part of the memory controller issuing a precharge command to the associated interleave of the interleaved memory, and wherein the current state indicator is further configured to indicate that the associated interleave of the interleaved memory is in a precharged state in response to the termination of the countdown cycle of the associated precharging timer.

16. The graphics system of claim 14, wherein the activate timer is further configured to begin a countdown cycle as part of the memory controller issuing an activate command to the associated interleave of the interleaved memory, and wherein the current state indicator is further configured to indicate that the associated interleave of the interleaved memory is in an active state in response to the termination of the countdown cycle of the associated activate timer.

17. The graphics system of claim 10, wherein the memory controller prioritizes commands issued to the interleaved memory, wherein commands which prepare an interleave of the interleaved memory for future access are assigned a higher priority than commands which read image data from an interleave of the interleaved memory.

18. A method for managing accesses to an image buffer, wherein the image buffer comprises a plurality of partitions, the method comprising:

a) maintaining a list of pending requests for data from the image buffer;

b) maintaining a status report for each partition of the image buffer;

c) testing the pending requests in the list of pending requests against the status report for each partition of the image buffer;

d) readying a first partition of the image buffer for access in response to determining that there is a first pending request for image data stored in the first partition and that the first partition is not ready for access; and

e) issuing a second pending request to the image buffer for image data stored in a second partition of the image buffer in response to determining that the second partition is ready for access;

wherein said issuing of the second pending request to the image buffer is performed while said readying of the first partition is in progress.

19. The method of claim 18, wherein (d) is performed only for the request for image data stored in the first partition least recently added to the list of pending requests.

20. The method of claim 18, wherein (d) is performed for each partition in the image buffer.

21. The method of claim 18, wherein readying the first partition of (d) comprises:

examining the status report associated with the first partition and determining the current state of the first partition ;

issuing a precharge command to the first partition if the associated status report indicates that the first partition is active;

issuing a activate command to the first partition if the associated status report indicates that the first partition is precharged; and

issuing no command to the first partition if the associated status report indicates that the first partition is precharging.

22. A method for reducing the number of idle states in a memory having a plurality of interleaves, the method comprising:

a) maintaining a list of pending requests for data from the interleaved memory;

b) assigning urgent priority to bringing a first interleave of the interleaved memory to a ready status in response to determining there is a first pending request for data from the first interleave and the first interleave is not in the ready status; and

c) independent of (b), issuing a second pending request for data to a second interleave in response to determining that the second interleave has the ready status.

23. The method of claim 22, further comprising:

determining a page address p associated with the first pending request for data from the first interleave; and

setting the active page of the first interleave to p as part of (b).

24. A method for managing accesses to an image buffer, wherein the image buffer comprises a plurality of partitions, the method comprising:

a) maintaining a list of pending requests for data from the image buffer;

b) maintaining a status report for each partition of the image buffer;

c) testing the pending requests in the list of pending requests against the status report for each partition of the image buffer;

d) readying a first partition of the image buffer for access in response to determining that there is a first pending request for image data stored in the first partition and that the first partition is not ready for access; and

e) issuing requests stored in the list of pending requests to the image buffer;

wherein readying the first partition of (d) comprises;

examining the status report associated with the first partition and determining the current state of the first partition;

issuing a precharge command to the first partition if the associated status report indicates that the first partition is active;

issuing a activate command to the first partition if the associated status report indicates that the first partition is precharged; and

issuing no command to the first partition if the associated status report indicates that the first partition is precharging.