SLM display data address mapping for four bank frame buffer

• US 6,741,503 B1
• Filed: 12/04/2002
• Issued: 05/25/2004
• Est. Priority Date: 12/04/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hearn, Alan, Farris, Jeffrey S.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Luu, Pho M.
• Application Number:
  US10/309,947
• Publication Number:
  US 20040109002A1
• Time in Patent Office: 538 Days
• Field of Search: 365/230.03, 365/230.08, 365/189.05
• US Class Current: 365/189.05
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/34 by control of light from an independent source
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

A method of addressing double buffered memory for an SLM, the memory address having only two bank bits. It is assumed that the pixel data is formatted into bit-planes, such that pixel positions in each bit plane can be identified. A bit plane bit is mapped to a first bank bit, and a pixel position bit is mapped to a second bank bit. The read/write bit is mapped to a column address bit. The remaining bit plane and pixel position bits are mapped to row address and column address bits.

Claims

1. A method of addressing double buffered memory for an SLM, the memory address having only two bank bits, the method comprising the steps of:

mapping a bit plane bit to a first bank bit;

mapping a pixel position bit to a second bank bit;

mapping a read/write bit to a column address bit; and

mapping the remaining bit plane and pixel position bits to row address and column address bits.

2. The method of claim 1, wherein the step of mapping a bit plane bit is performed by mapping the third bit plane bit.

3. The method of claim 1, wherein the step of mapping a pixel position bit is performed by mapping the fifth pixel position bit.

4. The method of claim 1, wherein the step of mapping a read/write bit is performed by mapping the bit to the most significant bit of the column address.

5. The method of claim 1, wherein the step of mapping a read/write bit is performed by mapping the bit to the second most significant bit of the column address.

6. The method of claim 1, wherein the four least significant bits of the pixel position bits are mapped to column address bits.

7. The method of claim 1, wherein the two least significant bits of the bit plane bits are mapped to column address bits.

8. The method of claim 1, wherein the two most significant bits of the bit plane bits are mapped to row address bits.

9. The method of claim 1, wherein the ten most significant bits of the pixel position bits are mapped to row address bits.