×

Semiconductor memory device with improved operation margin and increasing operation speed regardless of variations in semiconductor manufacturing processes

  • US 6,741,505 B2
  • Filed: 03/22/2002
  • Issued: 05/25/2004
  • Est. Priority Date: 09/27/2001
  • Status: Expired due to Fees
First Claim
Patent Images

1. A semiconductor memory device comprising:

  • a dummy bit line having a load equal to a load of a bit line;

    a reference voltage generating circuit generating a reference voltage;

    a comparator circuit comparing a potential of said dummy bit line with the reference voltage; and

    a timing signal generating circuit generating various kinds of timing signals based on an output of said comparator circuit, wherein said semiconductor memory device simultaneously selects a plurality of dummy memory cells and connects the selected dummy memory cells to said dummy bit line, and adjusts the potential of said dummy bit line.

View all claims
  • 4 Assignments
Timeline View
Assignment View
    ×
    ×