DRAM technology compatible processor/memory chips

• US 6,741,519 B2
• Filed: 07/09/2002
• Issued: 05/25/2004
• Est. Priority Date: 02/26/1999
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P., Cloud, Eugene H.
• Primary Examiner(s): Yoha, Connie C.
• Application Number:
  US10/191,329
• Publication Number:
  US 20020172089A1
• Time in Patent Office: 686 Days
• Field of Search: 365/230.06, 365/185.17, 365/149, 326/105, 326/106
• US Class Current: 365/230.06
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H03K 19/17716 with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register H03K19/17712 takes precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

The present invention includes a programmable logic array having a first logic plane that receives a number of input signals. The first logic plane has a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A number of non-volatile memory cells arranged in rows and columns of a second logic plane receive the outputs of the first logic plane and are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each non-volatile memory cell includes a MOSFET. Each non-volatile memory cell includes a stacked capacitor formed according to a DRAM process. Each non-volatile memory cell includes an electrical contact that couples the stacked capacitor to a gate of the MOSFET. The present invention also includes methods for producing the Ics and arrays.

Claims

1. An electronic system, comprising:

a memory; and

a processor coupled to the memory and formed on a die common with the memory; and

wherein the processor includes at least one programmable logic array including;

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor (MOSFET);

a stacked capacitor formed according to a dynamic random access memory (DRAM) process, wherein the stacked capacitor has a coupling ratio greater than 1.0.; and

an electrical contact that couples the stacked capacitor to a gate of the MOSFET.

2. The electronic system of claim 1, wherein the programmable logic array includes a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.

3. The electronic system of claim 2, wherein the first logic plane and the second logic plane each comprise NOR planes.

4. The electronic system of claim 1, wherein:

the processor includes at least one register formed front dynamic random access memory cells; and

wherein the processor includes at least one function and sequence circuit.

5. The electronic system of claim 1, wherein the processor includes a program circuit that stores a program.

6. The electronic system of claim 5, wherein the program circuit stores the program in an EEPROM.

7. The of electronic system claim 1, wherein the first logic plane includes N address lines and 2^N output lines.

8. An electronic system, comprising:

a memory; and

a processor coupled to the memory and formed on a die common with the memory; and

wherein the processor includes at least one programmable logic array including;

a logic plane that receives a number of input signals, the logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor;

a cup-shaped stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the transistor.

9. The electronic system of claim 8, wherein the implemented logical function includes at least one of NOR—

NOR, AND-OR, OR-AND, NAND—

NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.

10. The electronic system of claim 8, wherein the logic plane includes inverters adapted to generate complements of the input signals.

11. The electronic system of claim 8, wherein the electrical contact includes a polysilicon plug.

12. The electronic system of claim 8, wherein the stacked capacitor includes a fin type capacitor.

13. The electronic system of claim 8, wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.

14. The electronic system of claim 8, wherein the logic plane includes N address lines and 2^N output lines.

15. An electronic system, comprising:

a memory; and

a processor coupled to the memory and fanned on a die common with the memory; and

wherein the die includes at least one programmable logic array including;

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile first memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs; and

a second logic plane having a number of non-volatile second memory cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function,

wherein the first non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor;

a stacked capacitor formed according to a dynamic random access memory process, the capacitor providing a coupling ratio greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the transistor.

16. The electronic system of claim 15, wherein the implemented logical function includes at least one of NOR—

NOR, AND-OR, OR-AND, NAND—

NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-ANT).

17. The electronic system of claim 15, wherein the first logic plane includes inverters adapted to generate complements of the input signals.

18. The electronic system of claim 15, wherein the electrical contact includes a polysilicon plug.

19. The electronic system of claim 15, wherein the stacked capacitor includes a fin type capacitor.

20. The electronic system of claim 15, wherein the stacked capacitor includes a storage node, a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.

21. The electronic system of claim 15, wherein the first logic plane includes N address lines and 2^N output lines.

22. An electronic system, comprising:

a memory; and

a processor coupled to the memory and formed on a die common with the memory; and

wherein the processor includes at least one programmable logic array including;

a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and

wherein the non-volatile memory cells each include;

a metal oxide semiconductor field effect transistor (MOSFET) having a gate oxide, wherein the gate oxide has a thickness of less than 100 angstroms;

a stacked capacitor formed according to a dynamic random access memory (DRAM) process, the stacked capacitor being adapted to provide a coupling ratio of greater than 1.0; and

an electrical contact that couples the stacked capacitor to a gate of the MOSFET.

23. electronic system of claim 22, wherein the programmable logic array includes a second logic plane having a number of non-volatile memory cells arranged in rows and columns that receive the outputs of the first logic piano and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function.

24. The electronic system of claim 23, wherein the first logic plane and the second logic plane each comprise NOR planes.

25. The electronic system of claim 22, wherein the implemented logical function includes at least one NOR—

NOR, AND-OR, OR-AND, NAND—

NAND, NOR-OR, OR-NOR, AND-NOR, and NAND-AND.

26. The electronic system of claim 22, wherein:

the processor includes at least one register formed from dynamic random access memory cells; and

wherein the processor includes at least one function and sequence circuit.

27. The electronic system of claim 22, wherein the processor includes a program circuit that stores a program.

28. The electronic system of claim 27, wherein the program circuit stores the program in an EEPROM.

29. The electronic system of claims 22, wherein the gate oxide acts as a tunneling oxide.

30. The electronic system of claim 22, wherein the first logic plane includes inverters that are adapted to generate complements of the input signals.

31. The electronic system of claim 22, wherein the electrical contact includes a polysilicon plug.

32. The electronic system of claim 22, wherein the stacked capacitor includes a fin type capacitor.

33. The electronic system of claim 22, wherein the stacked capacitor includes a storage nod;

a capacitor dielectric, and a plate conductor and wherein the electrical contact couples the storage node of the stacked capacitor to the gate of the transistor.

34. The electronic system of claim 23, wherein the stacked capacitor includes a cap-shaped capacitor.