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DRAM technology compatible processor/memory chips

  • US 6,741,519 B2
  • Filed: 07/09/2002
  • Issued: 05/25/2004
  • Est. Priority Date: 02/26/1999
  • Status: Expired due to Term
First Claim
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1. An electronic system, comprising:

  • a memory; and

    a processor coupled to the memory and formed on a die common with the memory; and

    wherein the processor includes at least one programmable logic array including;

    a first logic plane that receives a number of input signals, the first logic plane having a plurality of non-volatile memory cells arranged in rows and columns that are interconnected to provide a number of logical outputs, and wherein the non-volatile memory cells each include;

    a metal oxide semiconductor field effect transistor (MOSFET);

    a stacked capacitor formed according to a dynamic random access memory (DRAM) process, wherein the stacked capacitor has a coupling ratio greater than 1.0.; and

    an electrical contact that couples the stacked capacitor to a gate of the MOSFET.

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