RF transmitters with saturation detection and correction and methods therefor

• US 6,741,840 B2
• Filed: 03/13/2002
• Issued: 05/25/2004
• Est. Priority Date: 03/13/2002
• Status: Active Grant

• Current Assignee: Motorola Mobility LLC (Lenovo Group Ltd.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Schwent, Dale, Nagode, Thomas, Pratt, Patrick
• Primary Examiner(s): Tran, Pablo N.
• Application Number:
  US10/097,714
• Publication Number:
  US 20030176170A1
• Time in Patent Office: 804 Days
• Field of Search: 455/126, 455/127, 455/115, 455/116, 455/63, 455/108, 455/75, 455/504, 455/561, 455/67.3, 330/149, 330/136, 330/129, 327/1, 327/297, 375/296, 375/297
• US Class Current: 455/126
• CPC Class Codes: H03F 1/0272 by using a signal derived from the output signal
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence

Abstract

Methods in radio communications devices having a transmitter with an integral control loop, and in other integral control systems, including generating a first error signal (210) based upon an amplifier output signal and a corrected reference signal, generating a second error (220) signal based on a closed loop integral control signal applied to a control input of the amplifier and based on an integral control reference signal, and generating the corrected reference signal (230) by correcting a reference signal based upon the first and second error signals.

Claims

1. A method in a radio communications device having a transmitter with an integral control loop, comprising:

generating a first error signal based upon an amplifier output signal and a corrected reference signal;

generating a second error signal based on a closed loop integral control signal applied to a control input of the amplifier and based on an integral control reference signal;

generating the corrected reference signal by correcting a reference signal based upon the first and second error signals.

2. The method of claim 1,

applying the closed loop integral control signal to the amplifier control input with an integral control device,

providing the first error signal to the integral control device,

generating the first error signal by subtracting the amplifier output signal from the corrected reference signal,

generating the second error signal only when the closed loop integral control signal is greater than the integral control reference signal;

correcting the reference signal by subtracting therefrom a quantity based upon the first and second error signals.

3. The method of claim 1, correcting the reference signal by subtracting therefrom an amount approximately equal to the first error signal.

4. The method of claim 1, correcting the reference signal by subtracting therefrom an amount greater than the first error signal.

5. The method of claim 1, correcting the reference signal by subtracting therefrom an amount less than the first error signal.

6. The method of claim 1, limiting the closed loop integral control signal applied to the amplifier control input if the closed loop integral control signal exceeds a limit set by the integral control reference signal.

7. The method of claim 1, correcting the reference signal based upon the first error signal, without regard for the second error signal, if the first error signal exceeds a saturation threshold.

8. The method of claim 7, limiting the closed loop integral control signal applied to the amplifier control input if the closed loop integral control signal exceeds a limit set by the integral control reference signal.

9. The method of claim 7, at least temporarily reducing the integral control reference signal limit if the first error signal exceeds the saturation threshold.

10. The method of claim 9, the transmitter operates in a burst transmission mode, maintaining the integral control reference signal at the reduced limit until the end of a transmission burst during which the limit was reduced, increasing the limit to a default value upon completion of the transmission burst during which the limit was reduce.

11. The method of claim 7, the integral control device comprises clocked accumulator and register circuits, inhibiting a clock of the integral control device if the first error signal exceeds the saturation threshold.

12. A method in a closed loop integral control system, comprising:

generating a first error signal based on an output signal of the controlled device and a corrected reference signal;

providing the first error signal to an integral control device applying a closed loop integral control signal to a control input of the controlled device,

generating a second error signal based on the closed loop integral control signal and based on an integral control reference signal;

generating the corrected reference signal by correcting a reference signal based upon the first and second error signals.

13. The method of claim 12,

generating the first error signal by subtracting the amplifier output signal from the corrected reference signal,

generating the second error signal only when the closed loop integral control signal is greater than the integral control reference signal;

correcting the reference signal by subtracting therefrom a quantity based upon the first and second error signals.

14. The method of claim 12, limiting the closed loop integral control signal if the closed loop integral control signal exceeds a limit set by the integral control reference signal.

15. The method of claim 12, correcting the reference signal based on the first error signal, without regard for the second error signal, if the first error signal exceeds a saturation threshold.

16. The method of claim 15, limiting the closed loop integral control signal if the closed loop integral control signal exceeds a limit set by the integral control reference signal.

17. The method of claim 15, at least temporarily reducing the integral control reference signal limit if the first error signal exceeds the saturation threshold.

18. The method of claim 15, the integral control device comprises clocked accumulator and register circuits, inhibiting a clock of the integral control device if the first error signal exceeds the saturation threshold.