Method and apparatus for operating a PLL with a phase detector/sample hold circuit for synthesizing high-frequency signals for wireless communications

• US 6,741,846 B1
• Filed: 11/08/2000
• Issued: 05/25/2004
• Est. Priority Date: 05/29/1998
• Status: Expired due to Term

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Wang, Caiyi, Welland, David R.
• Primary Examiner(s): Maung, Nay
• Assistant Examiner(s): Gesesse, Tilahun
• Application Number:
  US09/708,339
• Time in Patent Office: 1,294 Days
• Field of Search: 455/260, 455/255, 455/76, 455/165.1, 455/261, 455/265, 455/96, 455/75, 455/258, 455/256, 331/36.C, 331/36.R, 331/177.V
• US Class Current: 455/260
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/187 using means for coarse tuning the voltage controlled oscillator of the loop H03L7/191 - H03L7/195 take precedence
• CPC Class Codes: H03L 7/199 with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. During fine tuning adjustment, the PLL may include an analog control loop in which a phase detector circuit and sample and hold circuit are utilized. The output of the sample and hold circuit may be provided to the PLL VCO as VCO input control signals.

Claims

1. A frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator having an output frequency dependent upon a plurality of control signals, the plurality of control signals being received by the controllable oscillator as different frequency control input signals such that at least some of the plurality of control signals are configured to individually control the controllable oscillator without being combined with others of the plurality of control signals;

a phase detector configured to concurrently provide a plurality of analog output signals, the plurality of analog output signals being generated from a phase difference between at least two input signals; and

a sample and hold circuit coupled to sample each of the plurality analog output signals from the phase detector and to hold a plurality of sampled analog output signals, the sampled analog output signals being used to provide the plurality of control signals for the controllable oscillator;

wherein the controlled oscillator comprises a plurality of capacitor circuits connected in parallel to contribute a combined capacitance amount that determines at least in part the output frequency of the controlled oscillator, the plurality of control signals being coupled to control the amount of capacitance contributed by the plurality of capacitor circuits.

2. The frequency synthesizer of claim 1, wherein the input signals to the phase detector comprise a first input signal coupled to an output of the controllable oscillator and a second input signal coupled to a reference signal.

3. The frequency synthesizer of claim 1, wherein the input signals to the phase detector comprise a plurality of first input signals based upon an output of the controllable oscillator and at least one other second input signal coupled to a reference signal, the plurality of analog output signals being generated from the phase differences between the plurality of first input signals and the at least one other second input signal.

4. The frequency synthesizer of claim 3, wherein the number of first input signals and the number of analog output signals is equal.

5. The frequency synthesizer of claim 3, wherein the number of analog output signals is at least five.

6. The frequency synthesizer of claim 3, wherein the number of analog output signals is at least twenty.

7. The frequency synthesizer of claim 1, wherein the controlled oscillator comprises an LC tank resonant structure including the plurality of capacitor circuits.

8. The frequency synthesizer of claim 7, wherein the each of the plurality of capacitor circuits comprises at least one capacitor and a variable resistance element, the variable resistance element being coupled to at least one of the plurality of control signals.

9. The frequency synthesizer of claim 8, wherein the variable resistance element comprises a transistor and wherein at least one capacitor is coupled to the source or drain of the transistor and the control signal is coupled to the gate of the transistor.

10. The frequency synthesizer of claim 9, further comprising at least a second capacitor coupled between the source and drain of the transistor.

11. A frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator having an output frequency dependent upon a plurality of control signals, the plurality of control signals being received by the controllable oscillator as different frequency control input signals such that at least some of the plurality of control signals are configured to individually control the controllable oscillator without being combined with others of the plurality of control signals;

a phase detector configured to concurrently provide a plurality of analog output signals, the plurality of analog output signals being generated from a phase difference between at least two input signals; and

a sample and hold circuit coupled to sample each of the plurality analog output signals from the phase detector and to hold a plurality of sampled analog output signals, the sampled analog output signals being used to provide the plurality of control signals for the controllable oscillator;

wherein the input signals to the phase detector comprise a plurality of first input signals based upon an output of the controllable oscillator and at least one other second input signal coupled to a reference signal, the plurality of analog output signals being generated from the phase differences between the plurality of first input signals and the at least one other second input signal; and

wherein the plurality of first input signals are signals having at least one phase shifted edge with respect to each other.

12. The frequency synthesizer of claim 11, further comprising a shift register having the plurality of phase shifted signals as outputs.

13. A frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator having an output frequency dependent upon a plurality of control signals, the plurality of control signals being received by the controllable oscillator as different frequency control input signals such that at least some of the plurality of control signals are configured to individually control the controllable oscillator without being combined with others of the plurality of control signals;

a phase detector configured to concurrently provide a plurality of analog output signals, the plurality of analog output signals being generated from a phase difference between at least two input signals; and

a sample and hold circuit coupled to sample each of the plurality analog output signals from the phase detector and to hold a plurality of sampled analog output signals, the sampled analog output signals being used to provide the plurality of control signals for the controllable oscillator;

wherein the input signals to the phase detector comprise a plurality of first input signals based upon an output of the controllable oscillator and at least one other second input signal coupled to a reference signal, the plurality of analog output signals being generated from the phase differences between the plurality of first input signals and the at least one other second input signal; and

wherein the phase detector comprises a plurality of phase detector sub-circuits, each sub-circuit having as an output one of the plurality of analog output signals and having as inputs at least one of the plurality of first signals and at least one of the second signals.

14. The frequency synthesizer of claim 13, wherein there is only one second signal and each of the phase detector sub-circuits are coupled to receive this one second signal.

15. The frequency synthesizer of claim 13, wherein the number of phase detector sub-circuits and the number of first signals are equal.

16. The frequency synthesizer of claim 13, wherein each phase detector sub-circuit comprises a ramp capacitor coupled to a ramp voltage node and ramp voltage adjustment circuitry coupled to the ramp voltage node.

17. The frequency synthesizer of claim 16, wherein the ramp voltage adjustment circuitry comprises a switch coupled to the ramp voltage node and a logic gate having an output coupled to control the switch, the logic gate having the first and second signals as inputs and having an output indicative of a phase difference between the input signals.

18. The frequency synthesizer of claims 17, wherein the switch comprises a transistor coupled between the ramp voltage node and ground.

19. The frequency synthesizer of claim 17, further the ramp voltage adjustment circuitry further comprises a resistor coupled between the switch and the ramp voltage node.

20. The frequency synthesizer of claim 19, wherein the ramp voltage adjustment circuitry comprises a plurality of resistors connected in series to form a resistor string and a plurality of switches and logic circuits coupled to nodes within the resistor string, the logic circuits receiving select signals that operate to place one of the switches in an active mode thereby determining an amount of resistance provided by the resistor string and determining a rate of decay for the ramp voltage node.

21. The frequency synthesizer of claim 16, wherein each ramp voltage node within each phase detector sub-circuit are selectively coupled to a voltage source.

22. The frequency synthesizer of claim 21, wherein a plurality of the ramp voltage nodes of the phase detector sub-circuits are also selectively coupled to ground.

23. The frequency synthesizer of claim 16, wherein the sample and hold circuit comprises a plurality of switches and a plurality of hold capacitors, each hold capacitor being coupled to a hold voltage node, and each ramp voltage node of the phase detector sub-circuits being coupled through at least one of the switches to at least one of the hold voltage nodes, the hold voltage nodes being coupled to provide the plurality of sampled analog output signals from the sample and hold circuitry.

24. A frequency synthesizer having a phase locked loop, comprising:

a controllable oscillator having an output frequency dependent upon a plurality of control signals, the controlled oscillator comprising a plurality of capacitor circuits connected in parallel to contribute a combined capacitance amount that determines at least in part the output frequency of the controlled oscillator, the plurality of control signals being coupled to control the amount of capacitance contributed by the plurality of capacitor circuits;

a phase detector having a plurality of analog output signals, wherein the input signals to the phase detector comprise a plurality of first input signals based upon an output of the controllable oscillator and at least one other second input signal coupled to a reference signal, the plurality of analog output signals being generated from the phase differences between the first input signals and the second input signal, and wherein the phase detector comprises a plurality of phase detector sub-circuits, each sub-circuit having as inputs at least one of the plurality of first signals and at least one of the second signals, each sub-circuit comprising a ramp capacitor coupled to a ramp voltage node and ramp voltage adjustment circuitry coupled to the ramp voltage node and each sub-circuit having as an output one of the plurality of analog output signals; and

a sample and hold circuit coupled to sample the analog output signals from the phase detector and to hold a plurality of sampled analog output signals, the sampled analog output signals being used to provide the plurality of control signals for the controllable oscillator, wherein the sample and hold circuit comprises a plurality of switches and a plurality of hold capacitors, each hold capacitor being coupled to a hold voltage node, and each ramp voltage node of the phase detector sub-circuits being coupled through at least one of the switches to at least one of the hold voltage nodes, the hold voltage nodes being coupled to provide the plurality of sampled analog output signals from the sample and hold circuitry.

25. The frequency synthesizer of claim 24, wherein the number of phase shifted first input signals to the phase detector, the number of analog output signals from the phase detector, the number of sampled analog output signals, and the number of control signals is each greater than five.

26. The frequency synthesizer of claim 25, wherein the number of phase shifted first input signals to the phase detector, the number of analog output signals from the phase detector, the number of sampled analog output signals, and the number of control signals are equal.

27. A method of operating a frequency synthesizer having a phase locked loop and a controllable oscillator, comprising:

controlling an output frequency of a controllable oscillator utilizing at least in part a plurality of control signals, the plurality of control signals being received by the controllable oscillator as different frequency control input signals such that at least some of the plurality of control signals are configured to individually control the controllable oscillator without being combined with others of the plurality of control signals;

detecting a phase difference between at least two input signals to concurrently generate a plurality of analog output signals;

sampling and holding each of the plurality of analog output signals to produce a plurality of sampled analog output signals; and

using the plurality of sampled analog output signals to provide the plurality of control signals for the controllable oscillatory

wherein the controlled oscillator comprises a plurality of capacitor circuits connected in parallel to contribute a combined capacitance amount that determines at least in part the output frequency of the controlled oscillator, the plurality of control signals being coupled to control the amount of capacitance contributed by the plurality of capacitor circuits.

28. The method of claim 27, wherein the detecting step comprises detecting a phase difference between a plurality of first input signals based upon an output of the controllable oscillator and at least one other second input signal coupled to a reference signal, the plurality of analog output signals being generated from the phase differences between the plurality of first input signals and the at least one other second input signal.

29. The method of claim 28, wherein the number of first input signals and the number of analog output signals is equal.

30. The method of claim 28, wherein the number of analog output signals is at least five.

31. The method of claim 28, wherein the number of analog output signals is at least twenty.

32. The method of claim 27, wherein the controlled oscillator comprises an LC tank resonant structure including the plurality of capacitor circuits.

33. A method of operating a frequency synthesizer having a phase locked loop and a controllable oscillator, comprising:

controlling an output frequency of a controllable oscillator utilizing at least in part a plurality of control signals, the plurality of control signals being received by the controllable oscillator as different frequency control input signals such that at least some of the plurality of control signals are configured to individually control the controllable oscillator without being combined with others of the plurality of control signals;

detecting a phase difference between at least two input signals to concurrently generate a plurality of analog output signals;

sampling and holding each of the plurality of analog output signals to produce a plurality of sampled analog output signals; and

using the plurality of sampled analog output signals to provide the plurality of control signals for the controllable oscillator

wherein the detecting step comprises detecting a phase difference between a plurality of first input signals based upon an output of the controllable oscillator and at least one other second input signal coupled to a reference signal, the plurality of analog output signals being generated from the phase differences between the plurality of first input signals and the at least one other second input signal; and

wherein the plurality of first input signals are signals having at least one phase shifted edge with respect to each other.

34. A method of operating a frequency synthesizer having a phase locked loop and a controllable oscillator, comprising:

controlling an output frequency of a controllable oscillator utilizing at least in part a plurality of control signals, the plurality of control signals being received by the controllable oscillator as different frequency control input signals such that at least some of the plurality of control signals are configured to individually control the controllable oscillator without being combined with others of the plurality of control signals;

detecting a phase difference between at least two input signals to concurrently generate a plurality of analog output signals;

sampling and holding each of the plurality of analog output signals to produce a plurality of sampled analog output signals; and

using the plurality of sampled analog output signals to provide the plurality of control signals for the controllable oscillator

wherein the detecting step comprises detecting a phase difference between a plurality of first input signals based upon an output of the controllable oscillator and at least one other second input signal coupled to a reference signal, the plurality of analog output signals being generated from the phase differences between the plurality of first input signals and the at least one other second input signal; and

wherein the detecting step comprises utilizing a plurality of phase detector sub-circuits to determine the phase differences between the plurality of first signals and at least one of the second signals, each sub-circuit having as an output one of the plurality of analog output signals.

35. The method of claim 34, wherein the detecting step further comprises using the same second signal for each of the phase detector sub-circuits.

36. The method of 34, wherein each phase detector sub-circuit comprises a ramp capacitor coupled to a ramp voltage node and ramp voltage adjustment circuitry coupled to the ramp voltage node, the ramp voltage adjustment circuitry having at least one of the first signals and at least one of the second signals as inputs, and the ramp voltage nodes providing the plurality of analog output signals.

37. The method of claim 36, wherein the sample and hold circuit comprises a plurality of switches and a plurality of hold capacitors, each hold capacitor being coupled to a hold voltage node, and each ramp voltage node of the phase detector sub-circuits being coupled through at least one of the switches to at least one of the hold voltage nodes, the hold voltage nodes providing the plurality of sampled analog output signals.

38. The method of claim 37, wherein the detecting step comprises charging each ramp capacitor within each phase detector sub-circuit to a voltage level and decaying the voltage level with the ramp voltage adjustment circuitry for a first amount of time based upon a phase difference between the first and second input signals received by the ramp voltage adjustment circuitry, the charge on the ramp capacitors providing the plurality of analog control signals.

39. The method of claim 38, wherein the sampling and holding step comprises sharing charge between the ramp capacitors and the hold capacitors for a second amount of time, the charge on the hold capacitors providing the plurality of sampled analog control signals.