Accessory control interface

• US 6,742,061 B1
• Filed: 09/16/2002
• Issued: 05/25/2004
• Est. Priority Date: 03/08/2002
• Status: Active Grant

• Current Assignee: Nokia Technologies Oy (Nokia Corporation)
• Original Assignee: Nokia Corporation
• Inventors: Hellberg, Tino
• Primary Examiner(s): Dang, Khanh
• Application Number:
  US10/245,053
• Time in Patent Office: 617 Days
• Field of Search: 710/58, 710/60, 713/501, 713/502, 713/600, 327/152, 375/219
• US Class Current: 710/58
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: H04M 1/72409 by interfacing with external accessories hands-free H04M1/60
• CPC Class Codes: H04M 2201/10 Logic circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed is an interface (10, 40) between a master device (30) and a slave device (20). The interface includes a bit serial bidirectional signal line (10A) for conveying commands and associated data from the master device to the slave device, and for conveying a reset signal, an interrupt signal, and a learning sequence signal for specifying a duration of a bit time for data transferred from the slave device to the master device. The bit serial bidirectional signal line further indicates an accessory device connected/disconnected state to the master device.

Claims

1. An interface between a master device and a slave device, said interface comprising a bit serial bidirectional signal line for conveying commands and associated data from said master device to said slave device, said bit serial bidirectional signal line further conveying other signals, said other signals comprising a reset signal, an interrupt signal, and a learning sequence signal for specifying a duration of a bit time for data transferred from said slave device to said master device, where said interface comprises, in said slave device, an Accessory Control Interface chip and an oscillator providing a clock signal to said Accessory Control Interface chip, where the bit time is a multiple of the clock signal, and where said master device adapts the sampling of the data transferred from said slave device in accordance with the specified duration of the bit time.

2. An interface as in claim 1, where said master device is comprised of a personal digital assistant.

3. An interface as in claim 1, where said master device is comprised of a mobile terminal.

4. An interface as in claim 3, where said mobile terminal samples the data transferred from said slave device to said master device at a rate established by a mobile terminal sleep clock.

5. An interface as in claim 1, where said interface comprises, in said slave device, an Accessory Control Interface chip and a non-volatile memory for storing slave device related feature data that is readable by said master device over said bit serial bidirectional signal line in response to a memory read command sent from said master device to said Accessory Control Interface chip over said bit serial bidirectional signal line.

6. An interface as in claim 1, where said interface comprises, in said slave device, an Accessory Control Interface chip and a challenge/response authentication function that is challenged in response to an authentication challenge command and associated challenge data sent from said master device to said Accessory Control Interface chip over said bit serial bidirectional signal line, and where authentication result data is sent by said Accessory Control Interface chip to said master device over said bit serial bidirectional signal line in response to an authentication result command sent from said master device to said Accessory Control Interface chip over said bit serial bidirectional signal line.

7. An interface as in claim 1, where said bit serial bidirectional signal line further conveys a slave device connected/disconnected state to said master device.

8. An interface circuit for coupling a slave device to a master device, said interface circuit supporting a bit serial bidirectional signal line that conveys commands and associated data from said master device to said slave device, said bit serial bidirectional signal line further conveying other signals, said other signals comprising a reset signal, an interrupt signal, and a learning sequence signal for specifying a duration of a bit time for data transferred from said slave device to said master device, where said interface circuit comprises, in said slave device, an Accessory Control Interface chip and an oscillator providing a clock signal to said Accessory Control Interface chip, where the bit time is a multiple of the clock signal, and where said master device adapts the sampling of the data transferred from said slave device in accordance with the specified duration of the bit time.

9. An interface circuit as in claim 8, where said interface circuit is disposed within said slave device and comprises an oscillator for generating a clock signal, where the bit time is a multiple of the clock signal period, and where said master device samples said bit serial bidirectional signal line in accordance with the specified duration of the bit time.

10. An interface circuit as in claim 8, where said interface circuit is disposed within said slave device and comprises a non-volatile memory for storing slave device related feature data that is readable by said master device over said bit serial bidirectional signal line in response to a read command sent from said master device to said interface circuit over said bit serial bidirectional signal line.

11. An interface circuit as in claim 8, where said interface circuit is disposed within said slave device and comprises a challenge/response authentication function that is challenged in response to an authentication challenge command and associated challenge data received from said master device over said bit serial bidirectional signal line, and where authentication result data is sent to said master device over said bit serial bidirectional signal line in response to receiving an authentication result command from said master device over said bit serial bidirectional signal line.

12. An interface circuit as in claim 8, where said bit serial bidirectional signal line further conveys a slave device connected/disconnected state to said master device.

13. An interface circuit as in claim 8, where said master device is comprised of a mobile terminal.

14. An interface circuit as in claim 13, where said mobile terminal samples said bit serial bidirectional signal line at a rate established by a mobile terminal sleep clock.

15. An interface circuit as in claim 8, where said master device is comprised of a personal digital assistant.

16. An interface circuit for coupling a slave device to a master device, said interface circuit being disposed in said slave device and supporting a bit serial bidirectional signal line that conveys commands and associated data from said master device to said slave device, said bit serial bidirectional signal line further conveying other signals, said other signals comprising a reset signal, where said interface circuit comprises, in said slave device, an Accessory Control Interface chip and an oscillator providing a clock signal to said Accessory Control Interface chip, where the bit time is a multiple of the clock signal, and where said master device adapts the sampling of the data transferred from said slave device in accordance with the specified duration of the bit time.

17. An interface circuit as in claim 16, where said other signals further comprise an interrupt signal and a learning sequence signal for specifying a duration of a bit time for data transferred from said slave device to said master device.

18. An interface circuit for coupling a slave device to a master device, said interface circuit being disposed in said slave device and supporting a bit serial bidirectional signal line that conveys commands and associated data from said master device to said slave device, said bit serial bidirectional signal line further conveying other signals, said other signals comprising an interrupt signal, where said interface circuit comprises, in said slave device, an Accessory Control Interface chip and an oscillator providing a clock signal to said Accessory Control Interface chip, where the bit time is a multiple of the clock signal, and where said master device adapts the sampling of the data transferred from said slave device in accordance with the specified duration of the bit time.

19. An interface circuit as in claim 18, where said other signals further comprise a reset signal and a learning sequence signal for specifying a duration of a bit time for data transferred from said slave device to said master device.

20. An interface circuit for coupling a slave device to a master device, said interface circuit being disposed in said slave device and supporting a bit serial bidirectional signal line that conveys commands and associated data from said master device to said slave device, said bit serial bidirectional signal line further conveying other signals, said other signals comprising a learning sequence signal for specifying a duration of a bit time for data transferred from said slave device to said master device, where said interface circuit comprises, in said slave device, an Accessory Control Interface chip and an oscillator providing a clock signal to said Accessory Control Interface chip, where the bit time is a multiple of the clock signal, and where said master device adapts the sampling of the data transferred from said slave device in accordance with the specified duration of the bit time.

21. An interface circuit as in claim 20, where said interface circuit comprises an oscillator for generating a clock signal, where the duration of the bit time is a multiple of the clock signal period, and where said master device samples said bit serial bidirectional signal line in accordance with the specified duration of the bit time.

22. An interface circuit as in claim 21, where a logic zero and a logic one are distinguished by a presence or absence of a transition occurring on said bit serial bidirectional signal line by a predetermined point in the specified duration of the bit time.

23. An interface circuit as in claim 22, where the specified duration of the bit time is given by T, and where the predetermined point is about T/2.

24. An interface circuit as in claim 20, where said interface circuit comprises at least one register that is readable by said master device over said bit serial bidirectional signal line.

25. An interface circuit as in claim 20, where said interface circuit comprises at least one register that is writable by said master device over said bit serial bidirectional signal line.

26. An interface circuit as in claim 20, where said interface circuit comprises at least one memory device location that is readable by said master device over said bit serial bidirectional signal line.

27. An interface circuit as in claim 20, where said interface circuit comprises at least one memory device location that is writable by said master device over said bit serial bidirectional signal line.

28. An interface circuit as in claim 20, where said interface circuit comprises an authentication block that is addressable by commands sent by said master device over said bit serial bidirectional signal line, and that responds to at least one command with response data sent to said master device over said bit serial bidirectional signal line.

29. An interface circuit as in claim 20, where said other signals further comprise a reset signal and an interrupt signal.

30. A method for communicating between a master device and a slave device, comprising:

coupling the slave device to the master device through an interface, the interface comprising a bit serial bidirectional signal line;

sending a reset signal from the master device to the slave device over the bit serial bidirectional signal line;

sending a learning sequence signal to the master device over the bit serial bidirectional signal line for specifying a duration of a bit time for data transferred between the master device and the slave device; and

communicating at least one of data and commands between the master device and the slave device over the bit serial bidirectional signal line, wherein said interface comprises, in said slave device, an Accessory Control Interface chip and an oscillator providing a clock signal to said Accessory Control Interface chip, where the bit time is a multiple of the clock signal, and where said master device adapts the sampling of the data transferred from said slave device in accordance with the specified duration of the bit time.

31. A method as in claim 30, where communicating comprises the master device sampling the bit serial bidirectional signal line in accordance with the specified duration of the bit time.

32. A method as in claim 31, where a logic zero and a logic one are distinguished by a presence or absence of a transition occurring on the bit serial bidirectional signal line by a predetermined point in the specified duration of the bit time.

33. A method as in claim 32, where the specified duration of the bit time is given by T, and where the predetermined point is about T/2.