Dual-port buffer-to-memory interface

• US 6,742,098 B1
• Filed: 10/03/2000
• Issued: 05/25/2004
• Est. Priority Date: 10/03/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bonella, Randy M., Halbert, John B., Lam, Chung, Dodd, James M.
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Vital, Pierre M.
• Application Number:
  US09/678,751
• Time in Patent Office: 1,330 Days
• Field of Search: 711/5, 711/165, 711/171-172, 710/33, 710/307, 365/230.05
• US Class Current: 711/172
• CPC Class Codes: G06F 13/4256 using a clocked protocol

Abstract

Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 120:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

Claims

1. A memory system comprising:

a primary memory controller;

a memory data bus, having an effective bit-width m, coupled to the primary memory controller; and

at least one memory module coupled to the memory data bus, the memory module having a module data bus with an effective bit-width N=R×

m, where R is an integer value greater than one, the memory module comprising an interface circuit coupled between the memory data bus and the module data bus, the interface circuit capable of performing m-bit-wide data transfers on the memory data bus, the interface circuit capable of performing N-bit-wide data transfers on the module data bus,

the memory data bus comprising a point-to-point bus having one data bus segment connecting the primary memory controller and the first of the at least one memory modules, and one additional segment for each additional memory module, the additional segment connecting the additional memory module to the module immediately preceding it, and a ring data bus segment connecting the last of the memory modules in the memory system.

2. The memory system of claim 1, wherein the memory data bus and the module data bus each have a clock rate, the memory data bus clocking at a rate R times the clock rate of the module data bus.

3. A memory module comprising:

R ranks of memory devices, where R is at least two, each rank having an m-bit-wide data port;

a module data port capable of exchanging data signaling over a memory data bus having an effective bit-width m;

an interface circuit coupled between the module data port and the R memory-device-rank data ports, the interface circuit capable of performing m-bit-wide data transfers at the module data port, the interface circuit capable of performing R×

m-bit-wide data transfers with the R ranks of memory devices, the interface circuit comprising

R m-bit-wide data registers, each register capable of exchanging point-to-point data signaling with a corresponding rank of memory devices through the data port of that rank, and

a multiplexer, having a multiplexing ratio R, coupled between the R data registers and the external data port; and

a controller capable of synchronizing the operation of the interface circuit and the memory device ranks such that a data transfer comprising R serial data transfers on the memory data bus can be completed internal to the memory module with one R×

m-bit-wide data transfer with the memory device ranks.

4. The memory module of claim 3, wherein the controller supplies rank selection signals to the multiplexer and register latching signals to each of the data registers.

5. The memory module of claim 3, wherein data signaling between a data register and its rank of memory devices further comprises a bit mask received from the memory data bus along with a corresponding m bits, the multiplexer transferring the bit mask to the data register along with the corresponding m bits.

6. The memory module of claim 3, wherein the controller is capable of synchronizing the operation of the data registers, the module data port, and the multiplexer/demultiplexer in order to serialize data from a subset of the data registers onto the memory data bus.

7. The memory module of claim 3, wherein data transfers between one of the data registers and the corresponding rank of memory devices occurs at a clock rate related to the clock rate of the memory data bus by a factor 1/R.

8. The memory module of claim 3, where the module is a dual-inline memory module comprising a printed circuit board capable of connection to the memory data bus via insertion of the circuit board into a card edge connector connected to the memory data bus.

9. The memory module of claim 8, wherein R equals two, one of the two ranks of memory devices arranged on each side of the circuit board and connected to the corresponding data register via a set of module data signaling lines routed on the circuit board.

10. The memory module of claim 8, wherein the interface circuit comprises two interface circuits each serving half of the module data port and half of each rank of memory devices.

11. The memory module of claim 3, wherein the module data port comprises a dual-port buffer, each port of the dual-port buffer capable of connection to another memory module in a point-to-point configuration of memory data bus segments.

12. The memory module of claim 3, wherein data exchanges over the memory data bus comprise a data strobe signal, the module further comprising a data strobe circuit to generate data strobe signaling when transmitting data over the memory data bus.

13. The memory module of claim 12, wherein the controller begins an internal sequence of interface circuit write operations in response to an externally-supplied data strobe signal.

14. The memory module of claim 3, wherein data exchanges between the interface circuit and the ranks of memory devices comprise a data strobe signal, the module further comprising a data strobe circuit to generate data strobe signaling when transmitting data from the interface circuit to the ranks of memory devices, the interface circuit comprising a register circuit to latch data from the ranks of memory devices based on data strobe signaling received from those devices.

15. A memory module comprising:

R ranks of memory devices, where R is at least two, each rank having an m-bit-wide data port;

a module data port capable of exchanging data signaling over a memory data bus having an effective bit-width m;

an interface circuit coupled between the module data port and the R memory-device-rank data ports, the interface circuit capable of performing m-bit-wide data transfers at the module data port, the interface circuit capable of performing R×

m-bit-wide data transfers with the R ranks of memory devices; and

a controller capable of synchronizing the operation of the interface circuit and the memory device ranks such that a data transfer comprising R serial data transfers on the memory data bus can be completed internal to the memory module with one R×

m-bit-wide data transfer with the memory device ranks;

wherein the module data port comprises a dual-port buffer, each port of the dual-port buffer capable of connection to another memory module in a point-to-point configuration of memory data bus segments, wherein each port is capable of connection to an m-bit-wide memory data bus segment, wherein one port comprises a transfer port and the other port comprises a forwarding port, the module capable of using the transfer port to transfer data signals between the interface circuit and a higher-level controller connected to the memory data bus, the module capable of using the forwarding port to connect to a second memory module in order to transfer data signals between the transfer port on the first memory module and the transfer port on the second memory module.

16. A memory module comprising:

R ranks of memory devices, where R is at least two, each rank having an m-bit-wide data port;

a module data port capable of exchanging data signaling over a memory data bus having an effective bit-width m;

an interface circuit coupled between the module data port and the R memory-device-rank data ports, the interface circuit capable of performing m-bit-wide data transfers at the module data port, the interface circuit capable of performing R×

m-bit-wide data transfers with the R ranks of memory devices; and

a controller capable of synchronizing the operation of the interface circuit and the memory device ranks such that a data transfer comprising R serial data transfers on the memory data bus can be completed internal to the memory module with one R×

m-bit-wide data transfer with the memory device ranks,

wherein the module data port comprises a dual-port buffer, each port of the dual-port buffer capable of connection to another memory module in a point-to-point configuration of memory data bus segments, wherein each module data port is capable of connection to an m/2-bit-wide memory data bus segment, wherein the dual module data ports comprise first and second transfer/forwarding ports, the module capable of retransmitting data signals received at one of the transfer/forwarding ports, but not destined for that memory module, on the other transfer/forwarding port, the module also capable of transferring m/2 data signals between each of the transfer/forwarding ports and the interface circuit.

17. A method of host/memory communication comprising:

initiating a data access transaction, involving N data bits, between a memory controller and a memory module;

at the memory module, initiating a corresponding data access transaction between an interface circuit and R ranks of memory devices, each rank capable of m-bit-wide data transfers, R>

1;

transferring the N data bits between the memory controller and the memory module in m-bit-wide data segments; and

transferring the N data bits between the interface circuit and the R ranks of memory devices in M R×

m-bit-wide segments, where $M=\frac{N}{R\times <br><br>m}$

is an integer value,

wherein the method further comprises initiating a valid data access transaction when N is an integer multiple of m, but less than R×

m.

18. The method of claim 17, further comprising clocking transfers between the memory controller and the memory module at R times the rate that transfers are clocked between the interface circuit and the memory devices.

19. The method of claim 17, wherein when the data access transaction is a write transaction, transferring the N data bits between the interface circuit and N/m of the ranks of memory devices, while signaling the remainder of the ranks to ignore the write transaction.

20. The method of claim 17, wherein when the data access transaction is a read transaction, transferring R×

m data bits, including the N data bits requested for the read transaction, from the R ranks of memory devices to the interface circuit, and transferring the N data bits requested for the read transaction from the memory module to the memory controller.