MEMS wafer level package

• US 6,743,656 B2
• Filed: 07/23/2002
• Issued: 06/01/2004
• Est. Priority Date: 10/04/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Dewa, Andrew Steven, Lin, Tsen-Hwang, Orcutt, John W.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): VESPERMAN, WILLIAM C
• Application Number:
  US10/200,979
• Publication Number:
  US 20020179986A1
• Time in Patent Office: 679 Days
• Field of Search: 438/48, 438/51, 438/66, 438/68, 438/98, 438/24, 438/25, 438/28, 438/29, 257/414, 257/415, 257/532
• US Class Current: 438/66
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: G01P 1/023 for acceleration measuring devices
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/30107 Inductance

Abstract

An improved wafer level encapsulated micro-electromechanical device fabricated on a semiconductor wafer and a method of manufacture using state-of-the-art wafer fabrication and packaging technology. The device is contained within a hermetic cavity produced by bonding a silicon wafer with active circuits to an etched silicon wafer having cavities which surround each device, and bonding the two wafer by either thin film glass seal or by solder seal. The etched wafer and thin film sealing allow conductors to be kept to a minimum length and matched for improved electrical control of the circuit. Further, the device has capability for a ground ring in the solder sealed device. The devices may be packaged in plastic packages with wire bond technology or may be solder connected to an area array solder connected package.

Claims

1. A method comprising:

forming a micro-electromechanical wafer level encapsulated device, including the steps of;

providing a plurality of devices fabricated on a semiconductor substrate wafer having at least one conductor on the surface electrically coupled to each device,

providing a cap wafer fabricated from a silicon wafer, having an array of cavities of predetermined height etched in a pattern corresponding to the active devices on said substrate wafer where the area around the cavities are unetched areas, and a thin film of glass covering the unetched areas, and at least one hole fabricated in the cap wafer which provides access to each of said conductors,

aligning the semiconductor substrate wafer and the cap wafer,

heating to bond the cap wafer to the semiconductor substrate wafer using said thin film glass as a bonding agent such that each of the plurality of devices is sealed in a cavity of predetermined dimensions, and

sawing the now bonded cap wafer and semiconductor substrate wafer into individual chips.

2. A method as in claim 1 wherein cavities in said cap wafer are formed by anisotropic etching of silicon through a photolithographic pattern.

3. A method as in claim 1, wherein glass is deposited by sputtering through a mask having a predetermined pattern of apertures.

4. A method as in claim 1 wherein said thin film glass is patterned using photolithography and etching.

5. A method as in claim 1 wherein holes in said cap wafer are formed by anisotropic etching through a photolithographic pattern.

6. A method as in claim 1, wherein the devices are electrically tested prior to sawing the bonded cap wafer and semiconductor substrate wafer by positioning probes through holes in the cap wafer and contacting the conductors.

7. A method comprising:

forming micro-electromechanical wafer level encapsulated devices, including the steps of;

providing a plurality of devices fabricated on a semiconductor substrate wafer having at least one conductor on the surface electrically coupled to at least one of the plurality of devices,

providing a cap wafer fabricated from a silicon wafer, having an array of cavities of predetermined height etched in a pattern corresponding to each of the devices on said semiconductor substrate wafer where the area around the cavities are unetched areas, a layer of solder compatible metal and a layer of solder covering the unetched area, and a plurality of holes fabricated in the cap wafer which provides access to each of said conductors,

aligning the semiconductor substrate wafer and cap wafer,

bonding the cap wafer to the semiconductor substrate wafer using said solder and metals as bonding agents such that each of the plurality of descrete devices is sealed in a cavity of predetermined dimensions, and

sawing the now bonded cap wafer and semiconductor substrate wafer into individual devices.

8. A method as in claim 7 wherein said solder compatible metals and solder are deposited by sputtering through a mask having a predetermined pattern of apertures.

9. A method as in claim 7 wherein said solder is deposited by electroless plating.

10. A method comprising:

forming a micro-electromechanical wafer level encapsulated device, including the steps of;

providing a plurality of devices fabricated on a semiconductor substrate wafer having at least one conductor on the surface electrically coupled to each device,

providing a cap wafer fabricated from a silicon wafer, having an array of cavities of predetermined height etched in a pattern corresponding to the active devices on the semiconductor substrate wafer, and at least one hole fabricated in the cap wafer which provides access to each of said conductors,

aligning the semiconductor substrate wafer and cap wafer,

bonding the cap wafer to the semiconductor substrate wafer such that each of the plurality of devices is sealed in a cavity of predetermined dimensions, and sawing the now bonded cap wafer and semiconductor substrate wafer into individual chips.

11. A method as in claim 10 wherein cavities in said cap wafer are formed by anisotropic etching of silicon through a photolithographic pattern.

12. A method as in claim 10 wherein holes in said cap wafer are formed by anisotropic etching through a photolithographic pattern.

13. A method as in claim 10 wherein the devices are electrically tested prior to sawing the bonded cap wafer and semiconductor substrate wafer by positioning probes through holes in the cap wafer and contacting the conductors.