Polysilicon opening polish

• US 6,743,683 B2
• Filed: 12/04/2001
• Issued: 06/01/2004
• Est. Priority Date: 12/04/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Barns, Chris E., Doczy, Mark
• Primary Examiner(s): Norton, Nadine G.
• Assistant Examiner(s): DEO, DUY VU NGUYEN
• Application Number:
  US10/008,683
• Publication Number:
  US 20040038535A1
• Time in Patent Office: 910 Days
• Field of Search: 438/299, 438/301, 438/305, 438/306, 438/307, 438/592, 438/599, 438/706, 438/720, 438/721
• US Class Current: 438/299
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Fabricating a semiconductor structure includes providing a semiconductor substrate, forming a silicide layer over the substrate, and removing a portion of the silicide layer by chemical mechanical polishing. The fabrication of the structure can also include forming a dielectric layer after forming the silicide layer, and removing a portion of the dielectric layer by chemical mechanical polishing before removing the portion of the silicide layer.

Claims

1. A method for fabricating a semiconductor structure, comprising:

forming a silicide layer over a semiconductor substrate;

forming a dielectric layer over the silicide layer;

forming a top layer after forming the dielectric layer, the top layer comprising a titanium nitride layer;

removing a portion of the top layer;

removing a portion of the dielectric layer to expose a portion of the silicide layer; and

removing the portion of the silicide layer by chemical mechanical polishing;

wherein the portion of the top layer is removed before the portion of the dielectric layer is removed, and the portion of the dielectric layer is removed before the portion of the silicide layer is removed.

2. The method of claim 1, further comprising:

forming a high region and a low region on the semiconductor substrate,

wherein the high region and the low region are formed before the silicide layer is formed and the portion of the silicide layer removed by chemical mechanical polishing is removed from the high region.

3. The method of claim 2, wherein the high region is formed by depositing a polysilicon layer and removing a portion of the polysilicon layer.

4. The method of claim 3, wherein the silicide layer has a first chemical mechanical polishing rate, the polysilicon layer has a second chemical mechanical polishing rate, and the first chemical mechanical polishing rate is higher than the second chemical mechanical polishing rate.

5. The method of claim 1, wherein the dielectric layer comprises silicon dioxide.

6. The method of claim 1, wherein the dielectric layer comprises silicon nitride.

7. The method of claim 1, wherein the portion of the dielectric layer is removed by chemical mechanical polishing.

8. The method of claim 1, wherein the portion of the titanium nitride layer is removed by chemical mechanical polishing.

9. The method of claim 8, wherein the portion of the titanium nitride layer is removed with a first slurry and the portion of the dielectric layer is removed with a second slurry.

10. The method of claim 9, wherein a polishing rate of the titanium nitride layer with the first slurry is greater than a polishing rate of the dielectric layer with the first slurry.

11. The method of claim 9, wherein a polishing rate of the titanium nitride layer with the second slurry is less than a polishing rate of the dielectric layer with the second slurry.