Photoresist removal from alignment marks through wafer edge exposure

• US 6,743,735 B2
• Filed: 03/19/2002
• Issued: 06/01/2004
• Est. Priority Date: 03/19/2002
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chu, Po-Tao, Yang, Tai-Ming, Chen, Chung-Jen, Chen, Hsin-Yuan, Wu, Cheng-Ming
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Wilson, Christian D.
• Application Number:
  US10/102,288
• Publication Number:
  US 20030181058A1
• Time in Patent Office: 805 Days
• Field of Search: 438/462, 438/737, 438/738, 438/906
• US Class Current: 438/738
• CPC Class Codes: G03F 7/2026 for the removal of unwanted material, e.g. image or background correction
• CPC Class Codes: G03F 7/2028 of an edge bead on wafers
• CPC Class Codes: H01L 2223/54493 Peripheral marks on wafers, e.g. orientation flats, notches, lot number
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/906 Cleaning of wafer as interim step

Abstract

Removing photoresist from alignment marks on a semiconductor wafer using a wafer edge exposure process is disclosed. The alignment marks on the wafer are covered by photoresist used in conjunction with semiconductor processing of one or more layers deposited on the semiconductor wafer. One or more parts of the edge of the wafer are exposed to remove the photoresist from these parts and thus reveal alignment marks on the wafer. The exposure of the one or more parts of the wafer is accomplished without performing a photolithographic clear out process. Rather, a wafer edge exposure (WEE) process is inventively utilized. Once the WEE process is performed, subsequent layers may be deposited by aligning them using the revealed alignment marks.

Claims

1. A method comprising:

depositing one or more layers onto a semiconductor wafer having alignment marks on edges of the wafer; and

,

exposing the edges of the wafer both to clean the wafer for subsequent semiconductor processing and also to reveal the alignment marks on the edges of the wafer.

2. The method of claim 1, further comprising depositing one or more second layers on the semiconductor wafer, aligning the one or more second layers based on the alignment marks that are at the one or more parts of the edge of the wafer and that were revealed by exposing the one or more parts of the edge of the wafer.

3. The method of claim 2, wherein the one or more second layers comprise one or more of:

a metal layer, a silicon dioxide layer, and a silicon layer.

4. The method of claim 1, wherein the one or more layers comprise one or more of:

a metal layer, a silicon dioxide layer, and a silicon layer.

5. The method of claim 1, wherein exposing the one or more parts of the edge of the wafer comprises exposing a left part of the edge of the wafer and exposing a right part of the edge of the wafer.

6. The method of claim 1, wherein exposing the one or more parts of the edge of the wafer comprises exposing a lower-left part of the edge of the wafer and exposing an upper-right part of the edge of the wafer.

7. The method of claim 1, wherein exposing the one or more parts of the edge of the wafer comprises subjecting the one or more parts of the edge of the wafer to an ultraviolet light at a given dose.

8. The method of claim 1, wherein exposing the one or more parts of the edge of the wafer comprises utilizing a track production line.

9. A method comprising:

depositing one or more layers onto a semiconductor wafer having alignment marks on edges of the wafer; and

,

cleaning the edges of the wafer both to reveal the alignment marks on the edges of the wafer and also to prepare the wafer for subsequent semiconductor processing.

10. The method of claim 9, further comprising depositing one or more second layers on the semiconductor wafer, aligning the one or more second layers based on the alignment marks that are at the one or more parts of the edge of the wafer and from which the photoresist was removed.

11. The method of claim 9, wherein the one or more second layers comprise one or more of:

a metal layer, a silicon dioxide layer, and a silicon layer.

12. The method of claim 9, wherein the one or more layers comprise one or more of a metal layer, a silicon dioxide layer, and a silicon layer.

13. A semiconductor device formed at least in part by a method comprising:

depositing one or more layers onto a semiconductor wafer having alignment marks at least at an edge of the wafer; and

,

removing photoresist used in conjunction with processing of the one or more layers from one or more parts of the edge of the wafer both to reveal the alignment marks that are at the one or more parts of the edge of the wafer and also to clean the wafer for subsequent semiconductor processing.

14. The device of claim 13, wherein the method further comprises depositing one or more second layers on the semiconductor wafer, aligning the one or more second layers based on the alignment marks that are at the one or more parts of the edge of the wafer and from which the potoresist was removed.

15. The device of claim 13, wherein removing the photoresist from the one or more parts of the edge of the wafer comprises exposing the one or more parts of the edge of the wafer.

16. The device of claim 15, wherein exposing the one or more parts of the edge of the wafer comprises subjecting the one or more parts of the edge of the wafer to an ultraviolet light at a given dose.