Non-volatile memory using ferroelectric gate field-effect transistors

• US 6,744,087 B2
• Filed: 09/27/2002
• Issued: 06/01/2004
• Est. Priority Date: 09/27/2002
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Reohr, William Robert, Misewich, James A., Schrott, Alejandro Gabriel, Wang, Li-Kong
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US10/256,881
• Publication Number:
  US 20040061153A1
• Time in Patent Office: 613 Days
• Field of Search: 257/295, 257/328
• US Class Current: 257/295
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: H01L 29/40111 the electrodes comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H01L 29/6684 with a ferroelectric gate insulator
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H10B 51/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
• CPC Class Codes: H10B 51/30 characterised by the memory core region
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

A vertical ferroelectric gate field-effect transistor (FeGFET) device comprises a substrate and a first drain/source electrode formed on an upper surface of the substrate. An electrically conductive channel region is formed on an upper surface of the first drain/source electrode and electrically contacting the first drain/source electrode. The FeGFET device further comprises a ferroelectric gate region formed on at least one side wall of the channel region, at least one gate electrode electrically contacting the ferroelectric gate region, and a second drain/source electrode formed on an upper surface of the channel region and electrically contacting the channel region. The ferroelectric gate region is selectively polarizable in response to a potential applied between the gate electrode and at least one of the first and second drain/source electrodes. A non-volatile memory array can be formed comprising a plurality of FeGFET devices.

Claims

1. A semiconductor device, comprising:

a field-effect transistor (FET) formed on a silicon substrate, the FET including a drain region and a source region; and

a ferroelectric gate field-effect transistor (FeGFET) for storing a logical state of the semiconductor device, the FeGFET comprising;

a gate electrode formed on an upper surface of the substrate and in electrical contact with one of the drain region and the source region of the FET;

a ferroelectric gate dielectric layer formed on an upper surface of the gate electrode;

an electrically conductive channel layer formed on an upper surface of the ferroelectric gate dielectric layer; and

first and second drain/source electrodes, the first and second drain/source electrodes being formed on and electrically contacting the channel layer at laterally opposing ends of the channel layer;

wherein the ferroelectric gate dielectric layer is selectively polarizable in response to a potential applied between the gate electrode and at least one of the first and second drain/source electrodes.

2. The semiconductor device of claim 1, wherein the FeGFET is formed between at least two interconnection layers of the semiconductor device.

3. The semiconductor device of claim 1, further comprising an electrically conductive via formed on an upper surface of one of the drain region and the source region of the FET, the via electrically coupling the gate electrode of the FeGFET to one of the drain region and the source region of the FET.

4. A vertical ferroelectric gate field-effect transistor (FeGFET) device, comprising:

a substrate;

a first drain/source electrode formed on an upper surface of the substrate;

an electrically conductive channel region formed on an upper surface of the first drain/source electrode and electrically contacting the first drain/source electrode;

a ferroelectric gate region formed on at least one side wall of the channel region;

at least one gate electrode electrically contacting the ferroelectric gate region; and

a second drain/source electrode formed on an upper surface of the channel region and electrically contacting the channel region;

wherein the ferroelectric gate region is selectively polarizable in response to a potential applied between the gate electrode and at least one of the first and second drain/source electrodes.

5. The vertical FeGFET device of claim 4, further comprising a field-effect transistor (FET) formed in the substrate below the first drain/source electrode, the FET including a drain terminal and a source terminal, at least one of the drain and source terminals being electrically coupled to the first drain/source electrode.

6. The vertical FeGFET device of claim 4, wherein the channel region is substantially cylindrical, and the ferroelectric gate region is formed as at least a partial ring substantially surrounding an outer sidewall of the channel region.

7. The vertical FeGFET device of claim 4, further comprising:

a plug formed between the first and second drain/source terminals;

wherein the channel region is formed as at least a partial ring substantially surrounding the plug.

8. The vertical FeGFET device of claim 7, wherein the plug is formed of a substantially nonconductive material.

9. The vertical FeGFET device of claim 4, wherein the channel region is formed having a U-shaped cross-section substantially surrounding a plug.

10. The vertical FeGFET device of claim 4, wherein the FeGFET is disposed between a first interconnection layer and a second interconnection layer formed on the substrate.